From 10c0b86f83639535aaeedf3d90fe46e9dd779b9c Mon Sep 17 00:00:00 2001
From: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Date: Mon, 18 Dec 2023 11:16:12 +0100
Subject: [PATCH] soc: arm: use sys_cache* to enable caches for stm32f7 and
 stm32h7

Use sys_cache* functions to enable the caches for stm32f7 and
stm32h7. This ensures that CONFIG_CACHE_MANAGEMENT is
considered correctly.

Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
---
 soc/arm/st_stm32/stm32f7/soc.c    | 10 +++-------
 soc/arm/st_stm32/stm32h7/soc_m7.c | 10 +++-------
 2 files changed, 6 insertions(+), 14 deletions(-)

diff --git a/soc/arm/st_stm32/stm32f7/soc.c b/soc/arm/st_stm32/stm32f7/soc.c
index 19941c9cee0..4a9cc72a78d 100644
--- a/soc/arm/st_stm32/stm32f7/soc.c
+++ b/soc/arm/st_stm32/stm32f7/soc.c
@@ -12,6 +12,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
+#include <zephyr/cache.h>
 #include <soc.h>
 
 #include <cmsis_core.h>
@@ -30,13 +31,8 @@ static int st_stm32f7_init(void)
 	/* Enable ART Flash cache accelerator */
 	LL_FLASH_EnableART();
 
-	if (IS_ENABLED(CONFIG_ICACHE)) {
-		SCB_EnableICache();
-	}
-
-	if (IS_ENABLED(CONFIG_DCACHE)) {
-		SCB_EnableDCache();
-	}
+	sys_cache_instr_enable();
+	sys_cache_data_enable();
 
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 16 MHz from HSI */
diff --git a/soc/arm/st_stm32/stm32h7/soc_m7.c b/soc/arm/st_stm32/stm32h7/soc_m7.c
index 7ee62921c41..39c1d917c34 100644
--- a/soc/arm/st_stm32/stm32h7/soc_m7.c
+++ b/soc/arm/st_stm32/stm32h7/soc_m7.c
@@ -12,6 +12,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
+#include <zephyr/cache.h>
 #include <soc.h>
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
@@ -54,13 +55,8 @@ static int stm32h7_m4_wakeup(void)
  */
 static int stm32h7_init(void)
 {
-	if (IS_ENABLED(CONFIG_ICACHE)) {
-		SCB_EnableICache();
-	}
-
-	if (IS_ENABLED(CONFIG_DCACHE)) {
-		SCB_EnableDCache();
-	}
+	sys_cache_instr_enable();
+	sys_cache_data_enable();
 
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 64 MHz from HSI */