09ee834b4c
The Xilinx ZynqMP SoC embeds both Cortex-R "RPU" and Cortex-A "APU" cores. Since the current Zephyr architecture cannot support AMP of Cortex-R and Cortex-A within the same project, the RPU and APU should be considered separate platforms and handled accordingly. This commit re-purposes the SOC_XILINX_ZYNQMP symbol as a helper symbol indicating that Xilinx ZynqMP SoC is used, and adds a new symbol, SOC_XILINX_ZYNQMP_RPU, for specifying the actual build target platform. When Cortex-A support is added in the future, SOC_XILINX_ZYNQMP_APU symbol should be added and used to conditionally handle APU-specific code. For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
40 lines
850 B
Text
40 lines
850 B
Text
# Copyright (c) 2019 Lexmark International, Inc.
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# Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
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# SPDX-License-Identifier: Apache-2.0
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if SOC_XILINX_ZYNQMP
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config SOC
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default "xilinx_zynqmp"
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if SOC_XILINX_ZYNQMP_RPU
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config NUM_IRQS
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# must be >= the highest interrupt number used
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# - include the UART interrupts
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default 220
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config 2ND_LVL_ISR_TBL_OFFSET
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default 1
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config MAX_IRQ_PER_AGGREGATOR
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default 219
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config NUM_2ND_LEVEL_AGGREGATORS
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default 1
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 12000000
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endif # SOC_XILINX_ZYNQMP_RPU
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# Workaround for not being able to have commas in macro arguments
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DT_CHOSEN_Z_FLASH := zephyr,flash
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config FLASH_SIZE
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default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
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config FLASH_BASE_ADDRESS
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
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endif # SOC_XILINX_ZYNQMP
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