boards: arm: stm32: nucleo_h563zi enable can
Enable the FDCAN1 using pll1_q as clock source on pins TX/RX PD1/PD0. Using 160MHz pll1_q output with an additional can clk-divider, to allow other peripheral to use such a high clock source and to increase test coverage. Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
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@ -150,6 +150,8 @@ The Zephyr nucleo_h563zi board configuration supports the following hardware fea
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+===========+============+=====================================+
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| ADC | on-chip | ADC Controller |
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+-----------+------------+-------------------------------------+
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| CAN/CANFD | on-chip | CAN |
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+-----------+------------+-------------------------------------+
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| CLOCK | on-chip | reset and clock control |
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+-----------+------------+-------------------------------------+
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| DAC | on-chip | DAC Controller |
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@ -216,6 +218,7 @@ Default Zephyr Peripheral Mapping:
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- ADC1 channel 3 input: PA6
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- ADC1 channel 15 input: PA3
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- DAC1 channel 2 output: PA5
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- CAN/CANFD TX/RX: PD1/PD0
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- LD1 (green): PB0
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- LD2 (yellow): PF4
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- LD3 (red): PG4
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@ -152,6 +152,15 @@
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status = "okay";
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};
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&fdcan1 {
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pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_pd1>;
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pinctrl-names = "default";
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>,
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<&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>;
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clk-divider = <2>;
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status = "okay";
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};
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&flash0 {
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partitions {
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compatible = "fixed-partitions";
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@ -22,6 +22,7 @@
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zephyr,sram = &sram1;
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zephyr,flash = &flash0;
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zephyr,code-partition = &slot0_partition;
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zephyr,canbus = &fdcan1;
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};
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aliases {
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@ -11,6 +11,7 @@ supported:
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- gpio
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- arduino_serial
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- arduino_spi
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- can
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- gpio
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- uart
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- entropy
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