From 042d9ea38ad213cad912cdc4ca692084b385bb95 Mon Sep 17 00:00:00 2001 From: Thomas Stranger Date: Wed, 5 Apr 2023 15:30:37 +0200 Subject: [PATCH] boards: arm: stm32: nucleo_h563zi enable can Enable the FDCAN1 using pll1_q as clock source on pins TX/RX PD1/PD0. Using 160MHz pll1_q output with an additional can clk-divider, to allow other peripheral to use such a high clock source and to increase test coverage. Signed-off-by: Thomas Stranger --- boards/st/nucleo_h563zi/doc/index.rst | 3 +++ boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi | 9 +++++++++ boards/st/nucleo_h563zi/nucleo_h563zi.dts | 1 + boards/st/nucleo_h563zi/nucleo_h563zi.yaml | 1 + 4 files changed, 14 insertions(+) diff --git a/boards/st/nucleo_h563zi/doc/index.rst b/boards/st/nucleo_h563zi/doc/index.rst index e707e81fefa..ecb32665261 100644 --- a/boards/st/nucleo_h563zi/doc/index.rst +++ b/boards/st/nucleo_h563zi/doc/index.rst @@ -150,6 +150,8 @@ The Zephyr nucleo_h563zi board configuration supports the following hardware fea +===========+============+=====================================+ | ADC | on-chip | ADC Controller | +-----------+------------+-------------------------------------+ +| CAN/CANFD | on-chip | CAN | ++-----------+------------+-------------------------------------+ | CLOCK | on-chip | reset and clock control | +-----------+------------+-------------------------------------+ | DAC | on-chip | DAC Controller | @@ -216,6 +218,7 @@ Default Zephyr Peripheral Mapping: - ADC1 channel 3 input: PA6 - ADC1 channel 15 input: PA3 - DAC1 channel 2 output: PA5 +- CAN/CANFD TX/RX: PD1/PD0 - LD1 (green): PB0 - LD2 (yellow): PF4 - LD3 (red): PG4 diff --git a/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi b/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi index e3f3ae892b8..030bab86a0c 100644 --- a/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi +++ b/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi @@ -152,6 +152,15 @@ status = "okay"; }; +&fdcan1 { + pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_pd1>; + pinctrl-names = "default"; + clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>, + <&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>; + clk-divider = <2>; + status = "okay"; +}; + &flash0 { partitions { compatible = "fixed-partitions"; diff --git a/boards/st/nucleo_h563zi/nucleo_h563zi.dts b/boards/st/nucleo_h563zi/nucleo_h563zi.dts index 915a0ddee60..8acb70d0e6c 100644 --- a/boards/st/nucleo_h563zi/nucleo_h563zi.dts +++ b/boards/st/nucleo_h563zi/nucleo_h563zi.dts @@ -22,6 +22,7 @@ zephyr,sram = &sram1; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; + zephyr,canbus = &fdcan1; }; aliases { diff --git a/boards/st/nucleo_h563zi/nucleo_h563zi.yaml b/boards/st/nucleo_h563zi/nucleo_h563zi.yaml index 0130798df9d..56337bb12d0 100644 --- a/boards/st/nucleo_h563zi/nucleo_h563zi.yaml +++ b/boards/st/nucleo_h563zi/nucleo_h563zi.yaml @@ -11,6 +11,7 @@ supported: - gpio - arduino_serial - arduino_spi + - can - gpio - uart - entropy