michaelh/zephyr
1
0
Fork 0
Code Releases Activity

boards: arm: stm32: nucleo_h563zi enable can

Browse source 
Enable the FDCAN1 using pll1_q as clock source on pins TX/RX PD1/PD0.

Using 160MHz pll1_q output with an additional can clk-divider, to allow
other peripheral to use such a high clock source and to increase test
coverage.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit is contained in:
Thomas Stranger 2023-04-05 15:30:37 +02:00 • committed by Anas Nashif
commit 042d9ea38a
4 changed files with 14 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

3
boards/st/nucleo_h563zi/doc/index.rst
View file

@ -150,6 +150,8 @@ The Zephyr nucleo_h563zi board configuration supports the following hardware fea
+===========+============+=====================================+ +===========+============+=====================================+
| ADC | on-chip | ADC Controller | | ADC | on-chip | ADC Controller |
+-----------+------------+-------------------------------------+ +-----------+------------+-------------------------------------+
| CAN/CANFD | on-chip | CAN |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | reset and clock control | | CLOCK | on-chip | reset and clock control |
+-----------+------------+-------------------------------------+ +-----------+------------+-------------------------------------+
| DAC | on-chip | DAC Controller | | DAC | on-chip | DAC Controller |
@ -216,6 +218,7 @@ Default Zephyr Peripheral Mapping:
- ADC1 channel 3 input: PA6 - ADC1 channel 3 input: PA6
- ADC1 channel 15 input: PA3 - ADC1 channel 15 input: PA3
- DAC1 channel 2 output: PA5 - DAC1 channel 2 output: PA5
- CAN/CANFD TX/RX: PD1/PD0
- LD1 (green): PB0 - LD1 (green): PB0
- LD2 (yellow): PF4 - LD2 (yellow): PF4
- LD3 (red): PG4 - LD3 (red): PG4

9
boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi
View file

@ -152,6 +152,15 @@
status = "okay"; status = "okay";
}; };
&fdcan1 {
pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_pd1>;
pinctrl-names = "default";
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>,
<&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>;
clk-divider = <2>;
status = "okay";
};
&flash0 { &flash0 {
partitions { partitions {
compatible = "fixed-partitions"; compatible = "fixed-partitions";

1
boards/st/nucleo_h563zi/nucleo_h563zi.dts
View file

@ -22,6 +22,7 @@
zephyr,sram = &sram1; zephyr,sram = &sram1;
zephyr,flash = &flash0; zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition; zephyr,code-partition = &slot0_partition;
zephyr,canbus = &fdcan1;
}; };
aliases { aliases {

1
boards/st/nucleo_h563zi/nucleo_h563zi.yaml
View file

@ -11,6 +11,7 @@ supported:
- gpio - gpio
- arduino_serial - arduino_serial
- arduino_spi - arduino_spi
- can
- gpio - gpio
- uart - uart
- entropy - entropy