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boards: arm: stm32: nucleo_h563zi enable can

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Enable the FDCAN1 using pll1_q as clock source on pins TX/RX PD1/PD0.

Using 160MHz pll1_q output with an additional can clk-divider, to allow
other peripheral to use such a high clock source and to increase test
coverage.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit is contained in:
Thomas Stranger 2023-04-05 15:30:37 +02:00 • committed by Anas Nashif
commit 042d9ea38a
4 changed files with 14 additions and 0 deletions
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boards/st/nucleo_h563zi/doc/index.rst
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@ -150,6 +150,8 @@ The Zephyr nucleo_h563zi board configuration supports the following hardware fea
+===========+============+=====================================+
| ADC | on-chip | ADC Controller |
+-----------+------------+-------------------------------------+
| CAN/CANFD | on-chip | CAN |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | reset and clock control |
+-----------+------------+-------------------------------------+
| DAC | on-chip | DAC Controller |
@ -216,6 +218,7 @@ Default Zephyr Peripheral Mapping:
- ADC1 channel 3 input: PA6
- ADC1 channel 15 input: PA3
- DAC1 channel 2 output: PA5
- CAN/CANFD TX/RX: PD1/PD0
- LD1 (green): PB0
- LD2 (yellow): PF4
- LD3 (red): PG4