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tests: drivers: stm32 clock control testing on stm32l1 and stm32l0

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target is stm32l1/l0 with pll 32MHz from hsi clock config
target is stm32l1/l0 with pll 32MHz from hse clock config
target is stm32l1/l0 with hse clock config (no pll)
target is stm32l1/l0 with hsi clock config (no pll)
target is stm32l1/l0 with msi clock config (no pll)

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2022-02-28 16:25:17 +01:00 • committed by Maureen Helm
commit 02c3e9ac6f
5 changed files with 109 additions and 1 deletions
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21
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/hse_8.overlay Normal file
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@ -0,0 +1,21 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
status = "okay";
};
&rcc {
clocks = <&clk_hse>;
clock-frequency = <DT_FREQ_M(8)>;
};

21
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/msi_range6.overlay Normal file
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@ -0,0 +1,21 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_msi {
status = "okay";
msi-range = <6>;
};
&rcc {
clocks = <&clk_msi>;
clock-frequency = <4194304>;
ahb-prescaler = <1>;
};

28
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/pll_32_hse_8.overlay Normal file
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@ -0,0 +1,28 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
status = "okay";
};
&pll {
div = <2>;
mul = <8>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(32)>;
};

26
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/pll_32_hsi_16.overlay Normal file
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@ -0,0 +1,26 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi {
status = "okay";
};
&pll {
div = <2>;
mul = <4>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(32)>;
};

14
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/testcase.yaml
View file

@ -9,10 +9,22 @@ tests:
platform_allow: nucleo_g071rb nucleo_g474re platform_allow: nucleo_g071rb nucleo_g474re
drivers.stm32_clock_configuration.common.sysclksrc_hsi_16: drivers.stm32_clock_configuration.common.sysclksrc_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16.overlay" extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16.overlay"
platform_allow: nucleo_g071rb platform_allow: nucleo_g071rb nucleo_l152re nucleo_l073rz
drivers.stm32_clock_configuration.common.sysclksrc_hse_24: drivers.stm32_clock_configuration.common.sysclksrc_hse_24:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_24.overlay" extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_24.overlay"
platform_allow: nucleo_g474re platform_allow: nucleo_g474re
drivers.stm32_clock_configuration.common.sysclksrc_hse_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_8.overlay"
platform_allow: nucleo_l152re nucleo_l073rz
drivers.stm32_clock_configuration.common.sysclksrc_pll_170_hse_24: drivers.stm32_clock_configuration.common.sysclksrc_pll_170_hse_24:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16.overlay" extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16.overlay"
platform_allow: nucleo_g474re platform_allow: nucleo_g474re
drivers.stm32_clock_configuration.common.sysclksrc_pll_32_hse_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_32_hse_8.overlay"
platform_allow: nucleo_l152re nucleo_l073rz
drivers.stm32_clock_configuration.common.sysclksrc_pll_32_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_32_hsi_16.overlay"
platform_allow: nucleo_l152re nucleo_l073rz
drivers.stm32_clock_configuration.common.sysclksrc_msi_range6:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/msi_range6.overlay"
platform_allow: nucleo_l152re nucleo_l073rz