diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/hse_8.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/hse_8.overlay
new file mode 100644
index 00000000000..34e7988bc07
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/hse_8.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2022 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Warning: This overlay performs configuration from clean sheet.
+ * It is assumed that it is applied after clear_clocks.overlay file.
+ */
+
+&clk_hse {
+	hse-bypass;
+	clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&clk_hse>;
+	clock-frequency = <DT_FREQ_M(8)>;
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/msi_range6.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/msi_range6.overlay
new file mode 100644
index 00000000000..bb3994d6318
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/msi_range6.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2022 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Warning: This overlay performs configuration from clean sheet.
+ * It is assumed that it is applied after clear_clocks.overlay file.
+ */
+
+&clk_msi {
+	status = "okay";
+	msi-range = <6>;
+};
+
+&rcc {
+	clocks = <&clk_msi>;
+	clock-frequency = <4194304>;
+	ahb-prescaler = <1>;
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/pll_32_hse_8.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/pll_32_hse_8.overlay
new file mode 100644
index 00000000000..faa6a16288f
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/pll_32_hse_8.overlay
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2022 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Warning: This overlay performs configuration from clean sheet.
+ * It is assumed that it is applied after clear_clocks.overlay file.
+ */
+
+&clk_hse {
+	hse-bypass;
+	clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
+	status = "okay";
+};
+
+&pll {
+	div = <2>;
+	mul = <8>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(32)>;
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/pll_32_hsi_16.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/pll_32_hsi_16.overlay
new file mode 100644
index 00000000000..3af05ade1fb
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/pll_32_hsi_16.overlay
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2022 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Warning: This overlay performs configuration from clean sheet.
+ * It is assumed that it is applied after clear_clocks.overlay file.
+ */
+
+&clk_hsi {
+	status = "okay";
+};
+
+&pll {
+	div = <2>;
+	mul = <4>;
+	clocks = <&clk_hsi>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(32)>;
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common/testcase.yaml b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common/testcase.yaml
index 6b1d774b986..ab754c45097 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common/testcase.yaml
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common/testcase.yaml
@@ -9,10 +9,22 @@ tests:
     platform_allow: nucleo_g071rb nucleo_g474re
   drivers.stm32_clock_configuration.common.sysclksrc_hsi_16:
     extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16.overlay"
-    platform_allow: nucleo_g071rb
+    platform_allow: nucleo_g071rb nucleo_l152re nucleo_l073rz
   drivers.stm32_clock_configuration.common.sysclksrc_hse_24:
     extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_24.overlay"
     platform_allow: nucleo_g474re
+  drivers.stm32_clock_configuration.common.sysclksrc_hse_8:
+    extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_8.overlay"
+    platform_allow: nucleo_l152re nucleo_l073rz
   drivers.stm32_clock_configuration.common.sysclksrc_pll_170_hse_24:
     extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16.overlay"
     platform_allow: nucleo_g474re
+  drivers.stm32_clock_configuration.common.sysclksrc_pll_32_hse_8:
+    extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_32_hse_8.overlay"
+    platform_allow: nucleo_l152re nucleo_l073rz
+  drivers.stm32_clock_configuration.common.sysclksrc_pll_32_hsi_16:
+    extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_32_hsi_16.overlay"
+    platform_allow: nucleo_l152re nucleo_l073rz
+  drivers.stm32_clock_configuration.common.sysclksrc_msi_range6:
+    extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/msi_range6.overlay"
+    platform_allow: nucleo_l152re nucleo_l073rz