michaelh/zephyr
1
0
Fork 0
Code Releases Activity
zephyr/soc/nuvoton/npcx/npcx4/soc.h

61 lines
1.8 KiB
C
Raw Normal View History

soc: npcx: add soc drivers for npcx4 series This CL adds the soc drivers for npcx4 series. Besides adding npcx4m3f and npcx4m8f support, we also modified the register offset of LV_GPIO_CTL and PUPD_EN for npcx4 series. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-05-02 02:28:18 -07:00
/*
* Copyright (c) 2023 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _NUVOTON_NPCX_SOC_H_
#define _NUVOTON_NPCX_SOC_H_
soc: arm: fix missing configs & defines Some SoC have missing feature selections in their Kconfig. Some others are missing includes of CMSIS-Core headers. Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
2023-11-07 12:57:29 +00:00
#include <cmsis_core_m_defaults.h>
soc: npcx: add soc drivers for npcx4 series This CL adds the soc drivers for npcx4 series. Besides adding npcx4m3f and npcx4m8f support, we also modified the register offset of LV_GPIO_CTL and PUPD_EN for npcx4 series. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-05-02 02:28:18 -07:00
soc: arm: npcx: move soc-specific register definitions to soc.h This CL is to minimize `CONFIG_SOC_SERIES_XXXX` definitions when we introduce a new chip series. Most of them are relevant to register layouts in different npcx soc series. It moves soc-specific register definitions from `reg_def.h` to its own soc.h file. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-09-22 01:46:28 -07:00
/* NPCX4 SCFG multi-registers */
#define NPCX_DEVALT_OFFSET(n) (0x010 + n)
#define NPCX_PUPD_EN_OFFSET(n) (0x02b + n)
#define NPCX_LV_GPIO_CTL_OFFSET(n) (0x150 + n)
#define NPCX_DEVALT_LK_OFFSET(n) (0x210 + n)
/* NPCX4 MIWU multi-registers */
#define NPCX_WKEDG_OFFSET(n) (0x000 + (n * 0x010))
#define NPCX_WKAEDG_OFFSET(n) (0x001 + (n * 0x010))
#define NPCX_WKMOD_OFFSET(n) (0x002 + (n * 0x010))
#define NPCX_WKPND_OFFSET(n) (0x003 + (n * 0x010))
#define NPCX_WKPCL_OFFSET(n) (0x004 + (n * 0x010))
#define NPCX_WKEN_OFFSET(n) (0x005 + (n * 0x010))
#define NPCX_WKST_OFFSET(n) (0x006 + (n * 0x010))
#define NPCX_WKINEN_OFFSET(n) (0x007 + (n * 0x010))
/* NPCX4 ADC multi-registers */
#define NPCX_CHNDAT_OFFSET(n) (0x040 + n * 2)
#define NPCX_THRCTL_OFFSET(n) (0x080 + n * 2)
#define NPCX_THEN_OFFSET 0x090
#define THEN(base) (*(volatile uint16_t *)(base + NPCX_THEN_OFFSET))
/* NPCX4 ADC register fields */
#define NPCX_THRCTL_L_H 15
#define NPCX_THRCTL_CHNSEL FIELD(10, 5)
#define NPCX_THRCTL_THRVAL FIELD(0, 10)
/* NPCX4 FIU register fields */
#define NPCX_FIU_EXT_CFG_SPI1_2DEV 6
drivers: flash: npcx: add setting of low flash device This commit adds functions to select the low flash device and set the size of the low flash device. Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
2024-09-27 17:43:30 +08:00
#define NPCX_FIU_EXT_CFG_LOW_DEV_NUM 7
soc: arm: npcx: move soc-specific register definitions to soc.h This CL is to minimize `CONFIG_SOC_SERIES_XXXX` definitions when we introduce a new chip series. Most of them are relevant to register layouts in different npcx soc series. It moves soc-specific register definitions from `reg_def.h` to its own soc.h file. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-09-22 01:46:28 -07:00
/* NPCX4 supported group mask of DEVALT_LK */
#define NPCX_DEVALT_LK_GROUP_MASK \
(BIT(0) | BIT(2) | BIT(3) | BIT(4) | \
BIT(5) | BIT(6) | BIT(11) | BIT(13) | \
BIT(15) | BIT(16) | BIT(17) | BIT(18) | \
BIT(19) | BIT(21)) /* DEVALT0_LK - DEVALTN_LK */
/* NPCX4 Clock Configuration */
#define MAX_OFMCLK 120000000
soc: npcx: add soc drivers for npcx4 series This CL adds the soc drivers for npcx4 series. Besides adding npcx4m3f and npcx4m8f support, we also modified the register offset of LV_GPIO_CTL and PUPD_EN for npcx4 series. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-05-02 02:28:18 -07:00
soc: nuvoton: npcx: refactor npcx soc hierarchy for future chip support This commit refactors the NPCX SoC hierarchy to improve maintainability and enable future support for upcoming chips. Key changes include: 1. Introduced a new `npcxn` subdirectory under `common/` to consolidate shared components across the npcxn series. 2. Renamed and reorganized register access files for improved consistency. 3. Updated relevant Kconfig files, header files, and CMakeLists for the new structure. Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
2025-03-20 14:17:17 +08:00
#include "reg_def.h"
#include "clock_def.h"
soc: npcx: add soc drivers for npcx4 series This CL adds the soc drivers for npcx4 series. Besides adding npcx4m3f and npcx4m8f support, we also modified the register offset of LV_GPIO_CTL and PUPD_EN for npcx4 series. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-05-02 02:28:18 -07:00
#include <soc_dt.h>
drivers: espi: npcx: introduce espi taf driver This CL implements espi taf read/write/erase function for NPCX. Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
2023-12-08 17:25:35 +08:00
#include <soc_espi_taf.h>
soc: npcx: add soc drivers for npcx4 series This CL adds the soc drivers for npcx4 series. Besides adding npcx4m3f and npcx4m8f support, we also modified the register offset of LV_GPIO_CTL and PUPD_EN for npcx4 series. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-05-02 02:28:18 -07:00
#include <soc_pins.h>
#include <soc_power.h>
#endif /* _NUVOTON_NPCX_SOC_H_ */
Copy permalink