zephyr/arch/xtensa/soc/intel_s1000/dts.fixup

/* SoC level DTS fixup file */

#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE	NS16550_80800_CURRENT_SPEED

#define CONFIG_UART_NS16550_PORT_0_NAME		NS16550_80800_LABEL

#define L2_SRAM_BASE				CONFIG_SRAM_BASE_ADDRESS

#define L2_SRAM_SIZE				CONFIG_SRAM_SIZE_0 * 1024

#define CONFIG_I2C_0_BASE_ADDR			SNPS_DESIGNWARE_I2C_80400_BASE_ADDRESS

#define CONFIG_I2C_0_BITRATE			SNPS_DESIGNWARE_I2C_80400_CLOCK_FREQUENCY

#define CONFIG_I2C_0_NAME			SNPS_DESIGNWARE_I2C_80400_LABEL

#define CONFIG_I2C_0_IRQ			(SNPS_DESIGNWARE_I2C_80400_IRQ_0 << 16) | DW_ICTL_IRQ

#define CONFIG_I2C_0_IRQ_FLAGS			SNPS_DESIGNWARE_I2C_80400_IRQ_0_SENSE
/* End of SoC Level DTS fixup file */