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arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
/*
arc: abstract bulk of linker script The linker scripts for the quark_se_ss and generic_arc platforms are the exact same, so extract the contents in an includable file. Change-Id: I2cb90a6f819b12db77880228e41ff14c9755d59a Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2015-11-30 15:29:39 -05:00
* Copyright (c) 2014-2015 Wind River Systems, Inc.
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
*
license: Replace Apache boilerplate with SPDX tag Replace the existing Apache 2.0 boilerplate header with an SPDX tag throughout the zephyr code tree. This patch was generated via a script run over the master branch. Also updated doc/porting/application.rst that had a dependency on line numbers in a literal include. Manually updated subsys/logging/sys_log.c that had a malformed header in the original file. Also cleanup several cases that already had a SPDX tag and we either got a duplicate or missed updating. Jira: ZEP-1457 Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c Signed-off-by: David B. Kinder <david.b.kinder@intel.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-18 17:01:01 -08:00
* SPDX-License-Identifier: Apache-2.0
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
*/
arc: abstract bulk of linker script The linker scripts for the quark_se_ss and generic_arc platforms are the exact same, so extract the contents in an includable file. Change-Id: I2cb90a6f819b12db77880228e41ff14c9755d59a Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2015-11-30 15:29:39 -05:00
/**
* @brief Common parts of the linker scripts for the ARCv2/EM targets.
*/
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
#define _LINKER
#define _ASMLANGUAGE
#include <autoconf.h>
linker: move all linker headers to include/linker Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-17 11:30:47 -04:00
#include <linker/sections.h>
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
serial: nsim: Fix impossible-to-enable CONFIG_UART_NSIM CONFIG_UART_NSIM depends on CONFIG_NSIM, which was removed in commit 9bc69a46fa09 ("boards: Update arc em_starterkit support from 2.2 to 2.3"). Remove the dependency, and also remove the CONFIG_NSIM=y setting from the test_nsim test (which should now work). Also change the condition for EXTERN()ing _VectorTable in include/arch/arc/v2/linker.ld to check CONFIG_UART_NSIM instead of CONFIG_NSIM. I'm guessing the EXTERN() is there to make the symbol visible to nSIM, though I don't know anything about it. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-05-24 13:28:10 +02:00
#if defined(CONFIG_UART_NSIM)
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
EXTERN(_VectorTable)
#endif
linker: move all linker headers to include/linker Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-17 11:30:47 -04:00
#include <linker/linker-defs.h>
#include <linker/linker-tool.h>
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
arch: arc: Add the intial support of memory domain Refering the ARM's implementation, the initial support of memory domain in ARC is added: * changes in MPU drivers * changes in Kconfig * codes to configure memory domain during thread swap * changes in linker script template * memory domain related macro definitions the commited codes are simply tested through samples/mpu/mem_domain_apis_test. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-20 16:48:45 +08:00
#define KOBJECT_TEXT_AREA 256
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
/* physical address of RAM */
arc: unify copied linker script These files were almost exactly the same and had already started bit-rotting (note the missing net_l2 section in linker_harvard.ld) Issue: ZEP-528 Change-Id: I5039a2c1b86c5764a361b268c33ae8b17da1a9e0 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-09 11:45:23 -07:00
#ifdef CONFIG_HARVARD
#define ROMABLE_REGION ICCM
#define RAMABLE_REGION DCCM
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
#else
arc: unify copied linker script These files were almost exactly the same and had already started bit-rotting (note the missing net_l2 section in linker_harvard.ld) Issue: ZEP-528 Change-Id: I5039a2c1b86c5764a361b268c33ae8b17da1a9e0 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-09 11:45:23 -07:00
#if defined(CONFIG_XIP) && (FLASH_SIZE != 0)
#define ROMABLE_REGION FLASH
#define RAMABLE_REGION SRAM
#else
#define ROMABLE_REGION SRAM
#define RAMABLE_REGION SRAM
#endif
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
#endif
arch: arc: add user space support for arc * add the implementation of syscall * based on 'trap_s' intruction, id = 3 * add the privilege stack * the privilege stack is allocted with thread stack * for the kernel thread, the privilege stack is also a part of thread stack, the start of stack can be configured as stack guard * for the user thread, no stack guard, when the user stack is overflow, it will fall into kernel memory area which requires kernel privilege, privilege violation will be raised * modify the linker template and add MPU_ADDR_ALIGN * add user space corresponding codes in mpu * the user sp aux reg will be part of thread context * When user thread is interruptted for the 1st time, the context is saved in user stack (U bit of IRQ_CTLR is set to 1). When nest interrupt comes, the context is saved in thread's privilege stack * the arc_mpu_regions.c is moved to board folder, as it's board specific * the above codes have been tested through tests/kernel/mem_protect/ userspace for MPU version 2 Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-01-23 17:13:09 +08:00
#ifdef CONFIG_ARC_MPU_ENABLE
#if CONFIG_ARC_MPU_VER == 2
arch: arc: modify the linker template for APPLICAITON Memory The application memory area has a requirement of address alignment, especially when MPU requires power of 2. Modify the linker tmemplate to apply application memory address alignment generation Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-12 19:20:22 +08:00
#define MPU_MIN_SIZE 2048
arch: arc: add user space support for arc * add the implementation of syscall * based on 'trap_s' intruction, id = 3 * add the privilege stack * the privilege stack is allocted with thread stack * for the kernel thread, the privilege stack is also a part of thread stack, the start of stack can be configured as stack guard * for the user thread, no stack guard, when the user stack is overflow, it will fall into kernel memory area which requires kernel privilege, privilege violation will be raised * modify the linker template and add MPU_ADDR_ALIGN * add user space corresponding codes in mpu * the user sp aux reg will be part of thread context * When user thread is interruptted for the 1st time, the context is saved in user stack (U bit of IRQ_CTLR is set to 1). When nest interrupt comes, the context is saved in thread's privilege stack * the arc_mpu_regions.c is moved to board folder, as it's board specific * the above codes have been tested through tests/kernel/mem_protect/ userspace for MPU version 2 Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-01-23 17:13:09 +08:00
#elif CONFIG_ARC_MPU_VER == 3
arch: arc: modify the linker template for APPLICAITON Memory The application memory area has a requirement of address alignment, especially when MPU requires power of 2. Modify the linker tmemplate to apply application memory address alignment generation Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-12 19:20:22 +08:00
#define MPU_MIN_SIZE 32
arch: arc: add user space support for arc * add the implementation of syscall * based on 'trap_s' intruction, id = 3 * add the privilege stack * the privilege stack is allocted with thread stack * for the kernel thread, the privilege stack is also a part of thread stack, the start of stack can be configured as stack guard * for the user thread, no stack guard, when the user stack is overflow, it will fall into kernel memory area which requires kernel privilege, privilege violation will be raised * modify the linker template and add MPU_ADDR_ALIGN * add user space corresponding codes in mpu * the user sp aux reg will be part of thread context * When user thread is interruptted for the 1st time, the context is saved in user stack (U bit of IRQ_CTLR is set to 1). When nest interrupt comes, the context is saved in thread's privilege stack * the arc_mpu_regions.c is moved to board folder, as it's board specific * the above codes have been tested through tests/kernel/mem_protect/ userspace for MPU version 2 Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-01-23 17:13:09 +08:00
#endif
arch: arc: modify the linker template for APPLICAITON Memory The application memory area has a requirement of address alignment, especially when MPU requires power of 2. Modify the linker tmemplate to apply application memory address alignment generation Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-12 19:20:22 +08:00
#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );
arch: arc: add user space support for arc * add the implementation of syscall * based on 'trap_s' intruction, id = 3 * add the privilege stack * the privilege stack is allocted with thread stack * for the kernel thread, the privilege stack is also a part of thread stack, the start of stack can be configured as stack guard * for the user thread, no stack guard, when the user stack is overflow, it will fall into kernel memory area which requires kernel privilege, privilege violation will be raised * modify the linker template and add MPU_ADDR_ALIGN * add user space corresponding codes in mpu * the user sp aux reg will be part of thread context * When user thread is interruptted for the 1st time, the context is saved in user stack (U bit of IRQ_CTLR is set to 1). When nest interrupt comes, the context is saved in thread's privilege stack * the arc_mpu_regions.c is moved to board folder, as it's board specific * the above codes have been tested through tests/kernel/mem_protect/ userspace for MPU version 2 Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-01-23 17:13:09 +08:00
#else
arch: arc: modify the linker template for APPLICAITON Memory The application memory area has a requirement of address alignment, especially when MPU requires power of 2. Modify the linker tmemplate to apply application memory address alignment generation Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-12 19:20:22 +08:00
#define MPU_MIN_SIZE_ALIGN
arch: arc: add user space support for arc * add the implementation of syscall * based on 'trap_s' intruction, id = 3 * add the privilege stack * the privilege stack is allocted with thread stack * for the kernel thread, the privilege stack is also a part of thread stack, the start of stack can be configured as stack guard * for the user thread, no stack guard, when the user stack is overflow, it will fall into kernel memory area which requires kernel privilege, privilege violation will be raised * modify the linker template and add MPU_ADDR_ALIGN * add user space corresponding codes in mpu * the user sp aux reg will be part of thread context * When user thread is interruptted for the 1st time, the context is saved in user stack (U bit of IRQ_CTLR is set to 1). When nest interrupt comes, the context is saved in thread's privilege stack * the arc_mpu_regions.c is moved to board folder, as it's board specific * the above codes have been tested through tests/kernel/mem_protect/ userspace for MPU version 2 Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-01-23 17:13:09 +08:00
#endif
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
#if defined(CONFIG_XIP)
#define _DATA_IN_ROM __data_rom_start
#else
#define _DATA_IN_ROM
#endif
arc: unify copied linker script These files were almost exactly the same and had already started bit-rotting (note the missing net_l2 section in linker_harvard.ld) Issue: ZEP-528 Change-Id: I5039a2c1b86c5764a361b268c33ae8b17da1a9e0 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-09 11:45:23 -07:00
OUTPUT_ARCH(arc)
cmake: LD: Specify the entry point in the linker scripts The entry point can and therefore should be set by linker scripts. Whenever possible one should express things in the source language, be it .c or .ld, and not in code generators or in the build system. This patch removes the flag -eCONFIG_KERNEL_ENTRY from the linker's command line and replaces it with the linker script command ENTRY(CONFIG_KERNEL_ENTRY) Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-06-22 16:07:36 +02:00
ENTRY(CONFIG_KERNEL_ENTRY)
arc: unify copied linker script These files were almost exactly the same and had already started bit-rotting (note the missing net_l2 section in linker_harvard.ld) Issue: ZEP-528 Change-Id: I5039a2c1b86c5764a361b268c33ae8b17da1a9e0 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-09 11:45:23 -07:00
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
MEMORY {
arc: unify copied linker script These files were almost exactly the same and had already started bit-rotting (note the missing net_l2 section in linker_harvard.ld) Issue: ZEP-528 Change-Id: I5039a2c1b86c5764a361b268c33ae8b17da1a9e0 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-09 11:45:23 -07:00
#ifdef FLASH_START
FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_SIZE*1k
#endif
#ifdef ICCM_START
arc: ICCM memory should have read-write-execute attributes The ICCM memory, when present, can be both written and read, so changing the attributes to be read-write-execute. Change-Id: I432bd36f4a6ef632b7c4ce3bf8aa138895d52642 Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2017-01-09 14:50:00 -08:00
ICCM (rwx) : ORIGIN = ICCM_START, LENGTH = ICCM_SIZE*1k
arc: unify copied linker script These files were almost exactly the same and had already started bit-rotting (note the missing net_l2 section in linker_harvard.ld) Issue: ZEP-528 Change-Id: I5039a2c1b86c5764a361b268c33ae8b17da1a9e0 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-09 11:45:23 -07:00
#endif
#ifdef SRAM_START
arc: linker.ld modified to handle DRAM configuration as well For EM Starter Kit, one of the SOC choices has DRAM and no FLASH. If FLASH_SIZE is 0, the linker command file will create SRAM, ICCM and DCCM memories (and no FLASH). SRAM is really DRAM. Also, the linker.ld file is extended to handle microkernel objects. linker_harvard.ld has "all rights reserved". added to banner. Change-Id: Ia433578b94ce91722f3670819f44befafeecf878 Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-20 21:35:34 -07:00
SRAM (rwx) : ORIGIN = SRAM_START, LENGTH = SRAM_SIZE*1k
arc: unify copied linker script These files were almost exactly the same and had already started bit-rotting (note the missing net_l2 section in linker_harvard.ld) Issue: ZEP-528 Change-Id: I5039a2c1b86c5764a361b268c33ae8b17da1a9e0 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-09 11:45:23 -07:00
#endif
#ifdef DCCM_START
arc: linker.ld modified to handle DRAM configuration as well For EM Starter Kit, one of the SOC choices has DRAM and no FLASH. If FLASH_SIZE is 0, the linker command file will create SRAM, ICCM and DCCM memories (and no FLASH). SRAM is really DRAM. Also, the linker.ld file is extended to handle microkernel objects. linker_harvard.ld has "all rights reserved". added to banner. Change-Id: Ia433578b94ce91722f3670819f44befafeecf878 Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-20 21:35:34 -07:00
DCCM (rw) : ORIGIN = DCCM_START, LENGTH = DCCM_SIZE*1k
#endif
arc: enable gen_isr_tables mechanism Change-Id: I5897e110f554377796bfe38dd5c0f8652c29e5be Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 09:36:32 -08:00
/* Used by and documented in include/linker/intlist.ld */
IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
}
SECTIONS {
GROUP_START(ROMABLE_REGION)
SECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(1024)) {
arc-linker scripts: Add _image_[ram|rom]_[start|end] symbols Adds the following standard symbols to the arc linker scripts: _image_rom_start _image_rom_end _image_ram_start _image_ram_end Change-Id: Ib1dfa1dcb85140193557e72536145e74eb3ebb91 Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2015-10-30 12:50:11 -04:00
_image_rom_start = .;
arc-linker scripts: Replace __text_start/end symbols Standardizes on using symbol names _image_text_start and _image_text_end instead of __text_start and __text_end. Change-Id: I160ed6b4f117483fcffdfa04ce10bd6a5151704a Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2015-10-30 12:36:06 -04:00
_image_text_start = .;
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
/* when !XIP, .text is in RAM, and vector table must be at its very start */
KEEP(*(.exc_vector_table))
KEEP(*(".exc_vector_table.*"))
interrupts: use fixed section name for vector table Change-Id: Idfe330f7878fc59a6beb7aafd41eae076506ed3c Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-08 17:40:50 -08:00
KEEP(*(IRQ_VECTOR_TABLE))
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
arc: enable gen_isr_tables mechanism Change-Id: I5897e110f554377796bfe38dd5c0f8652c29e5be Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 09:36:32 -08:00
#ifdef CONFIG_GEN_SW_ISR_TABLE
KEEP(*(SW_ISR_TABLE))
#endif
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
*(.text)
*(".text.*")
build: Add C++ support Adds C++ support to the build system. Change-Id: Ice1e57a13598e7a48b0bf3298fc318f4ce012ee6 Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com> Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-01-13 13:02:56 -05:00
*(.gnu.linkonce.t.*)
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
arch: arc: Add the intial support of memory domain Refering the ARM's implementation, the initial support of memory domain in ARC is added: * changes in MPU drivers * changes in Kconfig * codes to configure memory domain during thread swap * changes in linker script template * memory domain related macro definitions the commited codes are simply tested through samples/mpu/mem_domain_apis_test. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-20 16:48:45 +08:00
#include <linker/kobject-text.ld>
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
} GROUP_LINK_IN(ROMABLE_REGION)
arch: arc: Add the intial support of memory domain Refering the ARM's implementation, the initial support of memory domain in ARC is added: * changes in MPU drivers * changes in Kconfig * codes to configure memory domain during thread swap * changes in linker script template * memory domain related macro definitions the commited codes are simply tested through samples/mpu/mem_domain_apis_test. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-20 16:48:45 +08:00
_image_text_end = .;
_image_rodata_start = .;
build: consolidate some common parts of linker scripts There are a number of data sections that are repeated across all the linker scripts for various architecture. In practice these don't always get updated and we have had problems with bit-rot. Consolidate these to make maintenance easier. x86 linker scripts now follow the same naming convention and we get rid of a linker-epilog.h that wasn't necessary and whose purpose has been lost to the mists of time. If applications want to define their own sections they should be allowed to. Linker scripts for x86 do not end with .h any more, they are not C header files even though we use C's preprocessor. Issue: ZEP-688 Change-Id: I893eb4619969695c1f980efd7c2ec9fa5dad136d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-10-20 08:09:32 -07:00
#include <linker/common-rom.ld>
build: Add C++ support Adds C++ support to the build system. Change-Id: Ice1e57a13598e7a48b0bf3298fc318f4ce012ee6 Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com> Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-01-13 13:02:56 -05:00
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) {
arc: move openocd_dbg section Its current placement was splitting the vector table in half. Move to rodata, a better place for it. There's no requirement for it to be in the text section. Change-Id: I67724b2a26a9cb62c2ccd473cb54c53e4f74dc32 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 15:40:08 -08:00
KEEP(*(.openocd_dbg))
KEEP(*(".openocd_dbg.*"))
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
*(.rodata)
*(".rodata.*")
build: Add C++ support Adds C++ support to the build system. Change-Id: Ice1e57a13598e7a48b0bf3298fc318f4ce012ee6 Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com> Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-01-13 13:02:56 -05:00
*(.gnu.linkonce.r.*)
build: x86: add some flexibility in custom linker scripts If a particular project needs to add additional data to the binary image, in most cases the entire linker script needs to forked into the project space, causing maintenance issues if the main linker script is changed. Now we add some Kconfig options to allow a project to specify some additional linker scripts which get included by the main one in a few key areas: 1) In the definition to the 'rodata' section, which can allow additional data to be included in this ROM section. 2) In the definition to the 'datas' section, which allows additional data to be included in this RAM section. 3) Arbitrary additional sections to be included at the end of the binary. For 1 and 2, this is useful to include data generated outside of the normal C compilation, such as data structures that are created by special build tools. 3 is useful for including arbitrary binary blobs inside the final image, such as for peripheral or co-processor firmware. Change-Id: I5738d3d6da25f5bc96cda8ae806bf1a3fb34bd5d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-11-21 14:16:11 -08:00
#ifdef CONFIG_CUSTOM_RODATA_LD
/* Located in project source directory */
#include <custom-rodata.ld>
#endif
arch: arc: Add the intial support of memory domain Refering the ARM's implementation, the initial support of memory domain in ARC is added: * changes in MPU drivers * changes in Kconfig * codes to configure memory domain during thread swap * changes in linker script template * memory domain related macro definitions the commited codes are simply tested through samples/mpu/mem_domain_apis_test. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-20 16:48:45 +08:00
#include <linker/kobject-rom.ld>
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
} GROUP_LINK_IN(ROMABLE_REGION)
arch: arc: Add the intial support of memory domain Refering the ARM's implementation, the initial support of memory domain in ARC is added: * changes in MPU drivers * changes in Kconfig * codes to configure memory domain during thread swap * changes in linker script template * memory domain related macro definitions the commited codes are simply tested through samples/mpu/mem_domain_apis_test. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-20 16:48:45 +08:00
_image_rodata_end = .;
arch: arc: modify the linker template for APPLICAITON Memory The application memory area has a requirement of address alignment, especially when MPU requires power of 2. Modify the linker tmemplate to apply application memory address alignment generation Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-12 19:20:22 +08:00
MPU_MIN_SIZE_ALIGN
arc-linker scripts: Add _image_[ram|rom]_[start|end] symbols Adds the following standard symbols to the arc linker scripts: _image_rom_start _image_rom_end _image_ram_start _image_ram_end Change-Id: Ib1dfa1dcb85140193557e72536145e74eb3ebb91 Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2015-10-30 12:50:11 -04:00
_image_rom_end = .;
arch: arc: add user space support for arc * add the implementation of syscall * based on 'trap_s' intruction, id = 3 * add the privilege stack * the privilege stack is allocted with thread stack * for the kernel thread, the privilege stack is also a part of thread stack, the start of stack can be configured as stack guard * for the user thread, no stack guard, when the user stack is overflow, it will fall into kernel memory area which requires kernel privilege, privilege violation will be raised * modify the linker template and add MPU_ADDR_ALIGN * add user space corresponding codes in mpu * the user sp aux reg will be part of thread context * When user thread is interruptted for the 1st time, the context is saved in user stack (U bit of IRQ_CTLR is set to 1). When nest interrupt comes, the context is saved in thread's privilege stack * the arc_mpu_regions.c is moved to board folder, as it's board specific * the above codes have been tested through tests/kernel/mem_protect/ userspace for MPU version 2 Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-01-23 17:13:09 +08:00
_image_rom_size = _image_rom_end - _image_rom_start;
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
GROUP_END(ROMABLE_REGION)
GROUP_START(RAMABLE_REGION)
arch: arc: Add the intial support of memory domain Refering the ARM's implementation, the initial support of memory domain in ARC is added: * changes in MPU drivers * changes in Kconfig * codes to configure memory domain during thread swap * changes in linker script template * memory domain related macro definitions the commited codes are simply tested through samples/mpu/mem_domain_apis_test. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-20 16:48:45 +08:00
#ifdef CONFIG_APPLICATION_MEMORY
SECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)
{
arch: arc: modify the linker template for APPLICAITON Memory The application memory area has a requirement of address alignment, especially when MPU requires power of 2. Modify the linker tmemplate to apply application memory address alignment generation Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-12 19:20:22 +08:00
MPU_MIN_SIZE_ALIGN
#include <app_data_alignment.ld>
arch: arc: Add the intial support of memory domain Refering the ARM's implementation, the initial support of memory domain in ARC is added: * changes in MPU drivers * changes in Kconfig * codes to configure memory domain during thread swap * changes in linker script template * memory domain related macro definitions the commited codes are simply tested through samples/mpu/mem_domain_apis_test. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-20 16:48:45 +08:00
__app_ram_start = .;
__app_data_ram_start = .;
arc-linker scripts: Add _image_[ram|rom]_[start|end] symbols Adds the following standard symbols to the arc linker scripts: _image_rom_start _image_rom_end _image_ram_start _image_ram_end Change-Id: Ib1dfa1dcb85140193557e72536145e74eb3ebb91 Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2015-10-30 12:50:11 -04:00
_image_ram_start = .;
arch: arc: Add the intial support of memory domain Refering the ARM's implementation, the initial support of memory domain in ARC is added: * changes in MPU drivers * changes in Kconfig * codes to configure memory domain during thread swap * changes in linker script template * memory domain related macro definitions the commited codes are simply tested through samples/mpu/mem_domain_apis_test. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-20 16:48:45 +08:00
APP_INPUT_SECTION(.data)
APP_INPUT_SECTION(".data.*")
__app_data_ram_end = .;
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
ARM: ARC: put sw_isr_table in ROM by default We can save a great deal of RAM this way, it only needs to be in RAM if dynamic interrupts are in use. At some point this config option broke, probably when static interrupts were introduced into the system. To induce build (instead of runtime) errors when irq_connect_dynamic() is used without putting the table in RAM, the dynamic interrupt functions are now conditionally compiled. Change-Id: I4860508746fd375d189390163876c59b6c544c9a Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-01-20 15:13:38 -08:00
arch: arc: Add the intial support of memory domain Refering the ARM's implementation, the initial support of memory domain in ARC is added: * changes in MPU drivers * changes in Kconfig * codes to configure memory domain during thread swap * changes in linker script template * memory domain related macro definitions the commited codes are simply tested through samples/mpu/mem_domain_apis_test. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-20 16:48:45 +08:00
__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);
build: x86: add some flexibility in custom linker scripts If a particular project needs to add additional data to the binary image, in most cases the entire linker script needs to forked into the project space, causing maintenance issues if the main linker script is changed. Now we add some Kconfig options to allow a project to specify some additional linker scripts which get included by the main one in a few key areas: 1) In the definition to the 'rodata' section, which can allow additional data to be included in this ROM section. 2) In the definition to the 'datas' section, which allows additional data to be included in this RAM section. 3) Arbitrary additional sections to be included at the end of the binary. For 1 and 2, this is useful to include data generated outside of the normal C compilation, such as data structures that are created by special build tools. 3 is useful for including arbitrary binary blobs inside the final image, such as for peripheral or co-processor firmware. Change-Id: I5738d3d6da25f5bc96cda8ae806bf1a3fb34bd5d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-11-21 14:16:11 -08:00
arch: arc: Add the intial support of memory domain Refering the ARM's implementation, the initial support of memory domain in ARC is added: * changes in MPU drivers * changes in Kconfig * codes to configure memory domain during thread swap * changes in linker script template * memory domain related macro definitions the commited codes are simply tested through samples/mpu/mem_domain_apis_test. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-20 16:48:45 +08:00
SECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)
{
__app_bss_start = .;
APP_INPUT_SECTION(.bss)
APP_INPUT_SECTION(".bss.*")
APP_INPUT_SECTION(COMMON)
__app_bss_end = .;
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
arch: arc: Add the intial support of memory domain Refering the ARM's implementation, the initial support of memory domain in ARC is added: * changes in MPU drivers * changes in Kconfig * codes to configure memory domain during thread swap * changes in linker script template * memory domain related macro definitions the commited codes are simply tested through samples/mpu/mem_domain_apis_test. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-20 16:48:45 +08:00
__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;
arc: linker.ld modified to handle DRAM configuration as well For EM Starter Kit, one of the SOC choices has DRAM and no FLASH. If FLASH_SIZE is 0, the linker command file will create SRAM, ICCM and DCCM memories (and no FLASH). SRAM is really DRAM. Also, the linker.ld file is extended to handle microkernel objects. linker_harvard.ld has "all rights reserved". added to banner. Change-Id: Ia433578b94ce91722f3670819f44befafeecf878 Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-20 21:35:34 -07:00
arch: arc: Add the intial support of memory domain Refering the ARM's implementation, the initial support of memory domain in ARC is added: * changes in MPU drivers * changes in Kconfig * codes to configure memory domain during thread swap * changes in linker script template * memory domain related macro definitions the commited codes are simply tested through samples/mpu/mem_domain_apis_test. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-20 16:48:45 +08:00
SECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)
{
APP_INPUT_SECTION(.noinit)
APP_INPUT_SECTION(".noinit.*")
arch: arc: modify the linker template for APPLICAITON Memory The application memory area has a requirement of address alignment, especially when MPU requires power of 2. Modify the linker tmemplate to apply application memory address alignment generation Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-12 19:20:22 +08:00
arch: arc: Add the intial support of memory domain Refering the ARM's implementation, the initial support of memory domain in ARC is added: * changes in MPU drivers * changes in Kconfig * codes to configure memory domain during thread swap * changes in linker script template * memory domain related macro definitions the commited codes are simply tested through samples/mpu/mem_domain_apis_test. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-20 16:48:45 +08:00
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
arch: arc: modify the linker template for APPLICAITON Memory The application memory area has a requirement of address alignment, especially when MPU requires power of 2. Modify the linker tmemplate to apply application memory address alignment generation Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-12 19:20:22 +08:00
__app_last_address_used = .;
/* Pad out application ram area to make MPU friendly */
SECTION_PROLOGUE(app_pad, (NOLOAD OPTIONAL),)
{
. = ALIGN(_app_data_align);
MPU_MIN_SIZE_ALIGN
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
arch: arc: Add the intial support of memory domain Refering the ARM's implementation, the initial support of memory domain in ARC is added: * changes in MPU drivers * changes in Kconfig * codes to configure memory domain during thread swap * changes in linker script template * memory domain related macro definitions the commited codes are simply tested through samples/mpu/mem_domain_apis_test. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-20 16:48:45 +08:00
__app_ram_end = .;
arch: arc: add user space support for arc * add the implementation of syscall * based on 'trap_s' intruction, id = 3 * add the privilege stack * the privilege stack is allocted with thread stack * for the kernel thread, the privilege stack is also a part of thread stack, the start of stack can be configured as stack guard * for the user thread, no stack guard, when the user stack is overflow, it will fall into kernel memory area which requires kernel privilege, privilege violation will be raised * modify the linker template and add MPU_ADDR_ALIGN * add user space corresponding codes in mpu * the user sp aux reg will be part of thread context * When user thread is interruptted for the 1st time, the context is saved in user stack (U bit of IRQ_CTLR is set to 1). When nest interrupt comes, the context is saved in thread's privilege stack * the arc_mpu_regions.c is moved to board folder, as it's board specific * the above codes have been tested through tests/kernel/mem_protect/ userspace for MPU version 2 Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-01-23 17:13:09 +08:00
__app_ram_size = __app_ram_end - __app_ram_start;
arch: arc: Add the intial support of memory domain Refering the ARM's implementation, the initial support of memory domain in ARC is added: * changes in MPU drivers * changes in Kconfig * codes to configure memory domain during thread swap * changes in linker script template * memory domain related macro definitions the commited codes are simply tested through samples/mpu/mem_domain_apis_test. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-20 16:48:45 +08:00
#endif /* CONFIG_APPLICATION_MEMORY */
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
arc: linker.ld: fix BSS section declaration The BSS section needs to use AT> in XIP systems otherwise the LMA addresses in the ELF binary are wrong, leading to issues if we try to manipulate the binary with objcopy. The GROUP_DATA_LINK_IN macro does the right thing here. This was already done on other arches but ARC was missed. Change-Id: I93748e919e0b68c1ff2dfb4b85b7064a8d980f3a Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 09:52:07 -08:00
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) {
arch: arc: modify the linker template for APPLICAITON Memory The application memory area has a requirement of address alignment, especially when MPU requires power of 2. Modify the linker tmemplate to apply application memory address alignment generation Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-12 19:20:22 +08:00
MPU_MIN_SIZE_ALIGN
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
/*
* For performance, BSS section is assumed to be 4 byte aligned and
* a multiple of 4 bytes
*/
. = ALIGN(4);
__bss_start = .;
arch: arc: Add the intial support of memory domain Refering the ARM's implementation, the initial support of memory domain in ARC is added: * changes in MPU drivers * changes in Kconfig * codes to configure memory domain during thread swap * changes in linker script template * memory domain related macro definitions the commited codes are simply tested through samples/mpu/mem_domain_apis_test. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-20 16:48:45 +08:00
#ifndef CONFIG_APPLICATION_MEMORY
_image_ram_start = .;
#endif
__kernel_ram_start = .;
KERNEL_INPUT_SECTION(.bss)
KERNEL_INPUT_SECTION(".bss.*")
KERNEL_INPUT_SECTION(COMMON)
*(".kernel_bss.*")
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
/*
* BSP clears this memory in words only and doesn't clear any
* potential left over bytes.
*/
__bss_end = ALIGN(4);
arc: linker.ld: fix BSS section declaration The BSS section needs to use AT> in XIP systems otherwise the LMA addresses in the ELF binary are wrong, leading to issues if we try to manipulate the binary with objcopy. The GROUP_DATA_LINK_IN macro does the right thing here. This was already done on other arches but ARC was missed. Change-Id: I93748e919e0b68c1ff2dfb4b85b7064a8d980f3a Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 09:52:07 -08:00
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),) {
/*
* This section is used for non-initialized objects that
* will not be cleared during the boot process.
*/
arch: arc: Add the intial support of memory domain Refering the ARM's implementation, the initial support of memory domain in ARC is added: * changes in MPU drivers * changes in Kconfig * codes to configure memory domain during thread swap * changes in linker script template * memory domain related macro definitions the commited codes are simply tested through samples/mpu/mem_domain_apis_test. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-20 16:48:45 +08:00
KERNEL_INPUT_SECTION(.noinit)
KERNEL_INPUT_SECTION(".noinit.*")
*(".kernel_noinit.*")
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
} GROUP_LINK_IN(RAMABLE_REGION)
arch: arc: Add the intial support of memory domain Refering the ARM's implementation, the initial support of memory domain in ARC is added: * changes in MPU drivers * changes in Kconfig * codes to configure memory domain during thread swap * changes in linker script template * memory domain related macro definitions the commited codes are simply tested through samples/mpu/mem_domain_apis_test. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-20 16:48:45 +08:00
SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,) {
/* when XIP, .text is in ROM, but vector table must be at start of .data */
__data_ram_start = .;
KERNEL_INPUT_SECTION(.data)
KERNEL_INPUT_SECTION(".data.*")
*(".kernel.*")
#ifdef CONFIG_CUSTOM_RWDATA_LD
/* Located in project source directory */
#include <custom-rwdata.ld>
#endif
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
__data_rom_start = LOADADDR(_DATA_SECTION_NAME);
#include <linker/common-ram.ld>
#include <linker/kobject.ld>
__data_ram_end = .;
arch: arc: modify the linker template for APPLICAITON Memory The application memory area has a requirement of address alignment, especially when MPU requires power of 2. Modify the linker tmemplate to apply application memory address alignment generation Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-12 19:20:22 +08:00
MPU_MIN_SIZE_ALIGN
arch: arc: add user space support for arc * add the implementation of syscall * based on 'trap_s' intruction, id = 3 * add the privilege stack * the privilege stack is allocted with thread stack * for the kernel thread, the privilege stack is also a part of thread stack, the start of stack can be configured as stack guard * for the user thread, no stack guard, when the user stack is overflow, it will fall into kernel memory area which requires kernel privilege, privilege violation will be raised * modify the linker template and add MPU_ADDR_ALIGN * add user space corresponding codes in mpu * the user sp aux reg will be part of thread context * When user thread is interruptted for the 1st time, the context is saved in user stack (U bit of IRQ_CTLR is set to 1). When nest interrupt comes, the context is saved in thread's privilege stack * the arc_mpu_regions.c is moved to board folder, as it's board specific * the above codes have been tested through tests/kernel/mem_protect/ userspace for MPU version 2 Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-01-23 17:13:09 +08:00
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
/* Define linker symbols */
arc-linker scripts: Add _image_[ram|rom]_[start|end] symbols Adds the following standard symbols to the arc linker scripts: _image_rom_start _image_rom_end _image_ram_start _image_ram_end Change-Id: Ib1dfa1dcb85140193557e72536145e74eb3ebb91 Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2015-10-30 12:50:11 -04:00
_image_ram_end = .;
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
_end = .; /* end of image */
arch: arc: Add the intial support of memory domain Refering the ARM's implementation, the initial support of memory domain in ARC is added: * changes in MPU drivers * changes in Kconfig * codes to configure memory domain during thread swap * changes in linker script template * memory domain related macro definitions the commited codes are simply tested through samples/mpu/mem_domain_apis_test. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-20 16:48:45 +08:00
__kernel_ram_end = .;
__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
arch: arc: Add the intial support of memory domain Refering the ARM's implementation, the initial support of memory domain in ARC is added: * changes in MPU drivers * changes in Kconfig * codes to configure memory domain during thread swap * changes in linker script template * memory domain related macro definitions the commited codes are simply tested through samples/mpu/mem_domain_apis_test. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-20 16:48:45 +08:00
GROUP_END(RAMABLE_REGION)
linker: move check for bad initlevels to the end of the sections This way, it does not fall in the middle of a group, like the RAM group and as a side-effect potentially move the dot (current address pointer). Change-Id: Iefbff8bbeadfc740dee61154d7db99b7b7aad6d6 Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2015-11-30 15:43:12 -05:00
build: x86: add some flexibility in custom linker scripts If a particular project needs to add additional data to the binary image, in most cases the entire linker script needs to forked into the project space, causing maintenance issues if the main linker script is changed. Now we add some Kconfig options to allow a project to specify some additional linker scripts which get included by the main one in a few key areas: 1) In the definition to the 'rodata' section, which can allow additional data to be included in this ROM section. 2) In the definition to the 'datas' section, which allows additional data to be included in this RAM section. 3) Arbitrary additional sections to be included at the end of the binary. For 1 and 2, this is useful to include data generated outside of the normal C compilation, such as data structures that are created by special build tools. 3 is useful for including arbitrary binary blobs inside the final image, such as for peripheral or co-processor firmware. Change-Id: I5738d3d6da25f5bc96cda8ae806bf1a3fb34bd5d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-11-21 14:16:11 -08:00
#ifdef CONFIG_CUSTOM_SECTIONS_LD
/* Located in project source directory */
#include <custom-sections.ld>
#endif
arc: enable gen_isr_tables mechanism Change-Id: I5897e110f554377796bfe38dd5c0f8652c29e5be Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 09:36:32 -08:00
#ifdef CONFIG_GEN_ISR_TABLES
#include <linker/intlist.ld>
#endif
arc: add support for generic Add support for a "generic" ARC implementation. This is a misnomer since ARC platforms are synthesized by the SOC vendor and are specifc to a given vendors implementation/configuration. This platform support if for an SOC where we are allowed to let the code to support the SOC into the wild but not allowed to name it in public. This change allows to work on support for the SOC in the open and let the rest of the community see the evolution of of the platform. Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 10:54:09 -07:00
}
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