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arc: add support for generic

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Add support for a "generic" ARC implementation. This is a misnomer
since ARC platforms are synthesized by the SOC vendor and are specifc
to a given vendors implementation/configuration.  This platform
support if for an SOC where we are allowed to let the code to support
the SOC into the wild but not allowed to name it in public.

This change allows to work on support for the SOC in the open and let
the rest of the community see the evolution of of the platform.

Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
This commit is contained in:
Dirk Brandewie 2015-09-10 10:54:09 -07:00 • committed by Anas Nashif
commit 8570e3cac2
12 changed files with 890 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

2
arch/arc/Kbuild
View file

@ -6,3 +6,5 @@ obj-y = core/
obj-y += prep_c.o \
reset.o \
vector_table.o
obj-$(CONFIG_PLATFORM_GENERIC_ARC) += platforms/generic/

13
arch/arc/Kconfig
View file

@ -40,6 +40,16 @@ source "kernel/Kconfig"
source "misc/Kconfig"
choice
prompt "Platform Selection"
default PLATFORM_GENERIC_ARC
config PLATFORM_GENERIC_ARC
bool "Minimum configuration for generic arc "
endchoice
menu "ARC EM4 processor options"
config CPU_ARCEM4
@ -235,6 +245,9 @@ config ARCH_HAS_NANO_FIBER_ABORT
endmenu
source "arch/arc/platforms/generic/Kconfig"
source "drivers/Kconfig"
source "net/Kconfig"

122
arch/arc/configs/nano_generic_defconfig Normal file
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@ -0,0 +1,122 @@
#
# Automatically generated file; DO NOT EDIT.
# Zephyr Kernel/arc Configuration
#
CONFIG_ARC=y
CONFIG_ARCH_DEFCONFIG="arch/arc/defconfig"
CONFIG_NANOKERNEL=y
# CONFIG_MICROKERNEL is not set
#
# General Kernel Options
#
CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000000
CONFIG_SYS_CLOCK_EXISTS=y
# CONFIG_INIT_STACKS is not set
CONFIG_XIP=y
# CONFIG_ENHANCED_SECURITY is not set
#
# Nanokernel Options
#
# CONFIG_BOOT_BANNER is not set
CONFIG_MAIN_STACK_SIZE=1024
CONFIG_ISR_STACK_SIZE=2048
# CONFIG_THREAD_CUSTOM_DATA is not set
# CONFIG_NANO_TIMEOUTS is not set
CONFIG_NANO_TIMERS=y
#
# General Setup
#
# CONFIG_EXPERIMENTAL is not set
CONFIG_CROSS_COMPILE=""
#
# Compile and Link Features
#
CONFIG_KERNEL_BIN_NAME="nanokernel"
# CONFIG_DEBUG is not set
CONFIG_COMPILER_OPT=""
CONFIG_TOOLCHAIN_VARIANT=""
CONFIG_MINIMAL_LIBC=y
# CONFIG_NEWLIB_LIBC is not set
#
# Debugging Options
#
# CONFIG_PRINTK is not set
# CONFIG_STDOUT_CONSOLE is not set
# CONFIG_ASSERT is not set
#
# Boot Options
#
# CONFIG_BOOTLOADER_UNKNOWN is not set
CONFIG_PLATFORM_GENERIC_ARC=y
#
# ARC EM4 processor options
#
CONFIG_CPU_ARCEM4=y
#
# ARCv2 Family Options
#
CONFIG_CPU_ARCV2=y
CONFIG_DATA_ENDIANNESS_LITTLE=y
CONFIG_NUM_IRQ_PRIO_LEVELS=2
CONFIG_NUM_REGULAR_IRQ_PRIO_LEVELS=1
CONFIG_NUM_IRQS=17
CONFIG_FIRQ_STACK_SIZE=1024
CONFIG_FAULT_DUMP=0
CONFIG_SW_ISR_TABLE=y
CONFIG_SW_ISR_TABLE_DYNAMIC=y
CONFIG_SW_ISR_TABLE_BSP=y
CONFIG_IRQ_VECTOR_TABLE_BSP=y
# CONFIG_ARCH_HAS_TASK_ABORT is not set
# CONFIG_ARCH_HAS_NANO_FIBER_ABORT is not set
CONFIG_PLATFORM="generic"
#
# generic arc BSP Options
#
CONFIG_RAM_START=0xa8000000
CONFIG_RAM_SIZE=0x14000
# CONFIG_NSIM is not set
#
# Device Drivers
#
# CONFIG_UART_SIMPLE is not set
# CONFIG_CONSOLE is not set
CONFIG_SERIAL=y
CONFIG_SERIAL_HAS_DRIVER=y
CONFIG_NS16550=y
# CONFIG_K20_UART is not set
# CONFIG_STELLARIS_UART is not set
# CONFIG_UART_INTERRUPT_DRIVEN is not set
#
# Interrupt Controllers
#
CONFIG_ARCV2_INTERRUPT_UNIT=y
#
# Timer Drivers
#
CONFIG_ARCV2_TIMER=y
#
# Random Generation Configuration
#
# CONFIG_RANDOM_GENERATOR is not set
# CONFIG_TEST_RANDOM_GENERATOR is not set
#
# Networking
#
# CONFIG_BLUETOOTH is not set
# CONFIG_NETWORKING is not set
CONFIG_DEFCONFIG_LIST="$ARCH_DEFCONFIG"

18
arch/arc/defconfig
View file

@ -11,7 +11,7 @@ CONFIG_NANOKERNEL=y
# General Kernel Options
#
CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=0
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000000
CONFIG_SYS_CLOCK_EXISTS=y
# CONFIG_INIT_STACKS is not set
CONFIG_XIP=y
@ -28,7 +28,7 @@ CONFIG_MAIN_STACK_SIZE=1024
CONFIG_ISR_STACK_SIZE=2048
# CONFIG_THREAD_CUSTOM_DATA is not set
# CONFIG_NANO_TIMEOUTS is not set
# CONFIG_NANO_TIMERS is not set
CONFIG_NANO_TIMERS=y
#
# General Setup
@ -56,6 +56,12 @@ CONFIG_MINIMAL_LIBC=y
#
# CONFIG_BOOTLOADER_UNKNOWN is not set
#
# ARC family options
#
CONFIG_ARC=y
CONFIG_PLATFORM_GENERIC_ARC=y
#
# ARC EM4 processor options
#
@ -77,6 +83,14 @@ CONFIG_SW_ISR_TABLE_BSP=y
CONFIG_IRQ_VECTOR_TABLE_BSP=y
# CONFIG_ARCH_HAS_TASK_ABORT is not set
# CONFIG_ARCH_HAS_NANO_FIBER_ABORT is not set
CONFIG_PLATFORM="generic"
#
# Generic arc BSP Options
#
CONFIG_RAM_START=0xa8000000
CONFIG_RAM_SIZE=0x14000
# CONFIG_NSIM is not set
#
# Device Drivers

56
arch/arc/platforms/generic/Kconfig Normal file
View file

@ -0,0 +1,56 @@
# generic ARC BSP configuration options
config PLATFORM
string
default generic
help
This option holds the directory name used by the build system
to locate the correct linker file.
config NUM_IRQ_PRIO_LEVELS
# This processor supports only 2 priority levels:
# 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs).
default 2
config NUM_REGULAR_IRQ_PRIO_LEVELS
# This processor supports only 1 Regular Interrupt priority level (1).
default 1
config NUM_IRQS
# must be >= the highest interrupt number used
default 17
menu "Generic BSP Options"
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32000000
config RAM_START
prompt "RAM start address"
hex
default 0x4000 if NSIM
default 0xa8000000
config RAM_SIZE
prompt "RAM size (in bytes)"
hex
default 0x4000 if NSIM
default 0x14000
config NSIM
prompt "Running on the MetaWare nSIM simulator"
bool
default n
help
For running on nSIM simulator.
a) Uses non-XIP to run in RAM.
b) Linked at address 0x4000 with 0x4000 of RAM so that it works with
a pc_size of 16 (default).
c) Sets the entry point to __reset, since it seems nSIM ignores the
reset vector when starting (??).
endmenu

10
arch/arc/platforms/generic/Makefile Normal file
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@ -0,0 +1,10 @@
ccflags-y +=-I$(srctree)/arch/arc/platforms/$(subst $(DQUOTE),,$(CONFIG_PLATFORM))
ccflags-y +=-I$(srctree)/include/drivers
ccflags-y +=-I$(srctree)/drivers
asflags-y +=-I$(srctree)/arch/arc/platforms/$(subst $(DQUOTE),,$(CONFIG_PLATFORM))
asflags-y := ${ccflags-y}
obj-y = system.o
obj-$(CONFIG_IRQ_VECTOR_TABLE_BSP) += irq_vector_table.o
obj-$(CONFIG_SW_ISR_TABLE_BSP) += sw_isr_table.o

166
arch/arc/platforms/generic/board.h Normal file
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@ -0,0 +1,166 @@
/* board.h - board configuration macros for the generic arc BSP */
/*
* Copyright (c) 2014-2015 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
This header file is used to specify and describe board-level aspects for the
generic arc BSP.
*/
#ifndef _BOARD__H_
#define _BOARD__H_
#include <misc/util.h>
/* default system clock */
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(32)
/* address bases */
#define PERIPH_ADDR_BASE_ADC 0x80015000 /* ADC */
#define PERIPH_ADDR_BASE_CREG_MST0 0x80018000 /* CREG Master 0 */
#define PERIPH_ADDR_BASE_CREG_SLV0 0x80018080 /* CREG Slave 0 */
#define PERIPH_ADDR_BASE_CREG_SLV1 0x80018180 /* CREG Slave 1 */
#define PERIPH_ADDR_BASE_GPIO0 0x80017800 /* GPIO 0 */
#define PERIPH_ADDR_BASE_GPIO1 0x80017900 /* GPIO 1 */
#define PERIPH_ADDR_BASE_I2C_MST0 0x80012000 /* I2C Master 0 */
#define PERIPH_ADDR_BASE_I2C_MST1 0x80012100 /* I2C Master 1 */
#define PERIPH_ADDR_BASE_SPI_MST0 0x80010000 /* SPI Master 0 */
#define PERIPH_ADDR_BASE_SPI_MST1 0x80010100 /* SPI Master 1 */
#ifdef CONFIG_NSIM
#define PERIPH_ADDR_BASE_UART0 0x4242 /* UART A */
#else
#define PERIPH_ADDR_BASE_UART0 0xB0002000 /* UART A */
#define PERIPH_ADDR_BASE_UART1 0xB0002400 /* UART B */
#endif
/* IRQs */
#define IRQ_TIMER0 16
#define IRQ_TIMER1 17
#define IRQ_I2C0_RX_AVAIL 18
#define IRQ_I2C0_TX_REQ 19
#define IRQ_I2C0_STOP_DET 20
#define IRQ_I2C0_ERR 21
#define IRQ_I2C1_RX_AVAIL 22
#define IRQ_I2C1_TX_REQ 23
#define IRQ_I2C1_STOP_DET 24
#define IRQ_I2C1_ERR 25
#define IRQ_SPI0_ERR_INT 26
#define IRQ_SPI0_RX_AVAIL 27
#define IRQ_SPI0_TX_REQ 28
#define IRQ_SPI1_ERR_INT 29
#define IRQ_SPI1_RX_AVAIL 30
#define IRQ_SPI1_TX_REQ 31
#define IRQ_ADC_IRQ 32
#define IRQ_ADC_ERR 33
#define IRQ_GPIO0_INTR 34
#define IRQ_GPIO1_INTR 35
#define IRQ_I2C_MST0_INTR 36
#define IRQ_I2C_MST1_INTR 37
#define IRQ_SPI_MST0_INTR 38
#define IRQ_SPI_MST1_INTR 39
#define IRQ_SPI_SLV_INTR 40
#define IRQ_UART0_INTR 41
#define IRQ_UART1_INTR 42
#define IRQ_I2S_INTR 43
#define IRQ_GPIO_INTR 44
#define IRQ_PWM_TIMER_INTR 45
#define IRQ_USB_INTR 46
#define IRQ_RTC_INTR 47
#define IRQ_WDOG_INTR 48
#define IRQ_DMA_CHAN0 49
#define IRQ_DMA_CHAN1 50
#define IRQ_DMA_CHAN2 51
#define IRQ_DMA_CHAN3 52
#define IRQ_DMA_CHAN4 53
#define IRQ_DMA_CHAN5 54
#define IRQ_DMA_CHAN6 55
#define IRQ_DMA_CHAN7 56
#define IRQ_MAILBOXES_INTR 57
#define IRQ_COMPARATORS_INTR 58
#define IRQ_SYS_PMU_INTR 59
#define IRQ_DMA_CHANS_ERR 60
#define IRQ_INT_SRAM_CTLR 61
#define IRQ_INT_FLASH0_CTLR 62
#define IRQ_INT_FLASH1_CTLR 63
#define IRQ_ALWAYS_ON_TMR 64
#define IRQ_ADC_PWR 65
#define IRQ_ADC_CALIB 66
#define IRQ_ALWAYS_ON_GPIO 67
#ifndef _ASMLANGUAGE
#define EXC_FROM_IRQ(irq) ((irq) + 16)
#define VECTOR_FROM_IRQ(irq) EXC_FROM_IRQ(irq)
#define VECTOR_ADDR(vector) ((uint32_t *)((int)vector << 2))
#include <misc/util.h>
#include <drivers/rand32.h>
/* ARCv2 timer 0 configuration settings for the system clock */
#ifdef CONFIG_NANOKERNEL
#define CONFIG_ARCV2_TIMER0_CLOCK_FREQ 32000000 /* 32MHz reference clock \
*/
#define CONFIG_ARCV2_TIMER1_CLOCK_FREQ CONFIG_ARCV2_TIMER0_CLOCK_FREQ
#endif /* CONFIG_NANOKERNEL */
#define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
#define CONFIG_ARCV2_TIMER0_INT_PRI 0
#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
#define CONFIG_ARCV2_TIMER1_INT_PRI 1
/*
* UART configuration settings
*
* This BSP only supports the nanokernel. Therefore:
* - only polled mode is supported (interrupt-driven mode is NOT supported); and
* - only the target console is supported (hostserver driver is NOT supported).
*/
#define CONFIG_UART_CONSOLE_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
#define CONFIG_UART_CONSOLE_BAUDRATE 115200
#define CONFIG_UART_CONSOLE_REGS PERIPH_ADDR_BASE_UART0
#define CONFIG_UART_CONSOLE_IRQ IRQ_UART0_INTR
#define CONFIG_UART_CONSOLE_INT_PRI 0
#define UART_REG_ADDR_INTERVAL 4 /* for ns16550 driver */
#endif /* !_ASMLANGUAGE */
#endif /* _BOARD__H_ */

216
arch/arc/platforms/generic/generic.cmd Normal file
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@ -0,0 +1,216 @@
/* linker.cmd - Linker command/script file */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
Linker script for the Generic ARC BSPs.
*/
#define _LINKER
#define _ASMLANGUAGE
#include <autoconf.h>
#include <sections.h>
#if defined(CONFIG_NSIM)
#define KENTRY __reset
EXTERN(_VectorTable)
#else
#define KENTRY _VxMicroStart
#endif
#include <linker-tool.h>
#define INIT_LEVEL(level) \
__initconfig##level##_start = .; \
*(.initconfig##level##.init) \
/* physical address of RAM */
#ifdef CONFIG_XIP
#define ROMABLE_REGION FLASH
#define RAMABLE_REGION SRAM
#else
#define ROMABLE_REGION SRAM
#define RAMABLE_REGION SRAM
#endif
#if defined(CONFIG_XIP)
#define _DATA_IN_ROM __data_rom_start
#else
#define _DATA_IN_ROM
#endif
MEMORY {
FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_SIZE
SRAM (wx) : ORIGIN = SRAM_START, LENGTH = SRAM_SIZE
DCCM (wx) : ORIGIN = DCCM_START, LENGTH = DCCM_SIZE
}
SECTIONS {
GROUP_START(ROMABLE_REGION)
SECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(1024)) {
__text_start = .;
/* when !XIP, .text is in RAM, and vector table must be at its very start */
KEEP(*(.exc_vector_table))
KEEP(*(".exc_vector_table.*"))
KEEP(*(.irq_vector_table))
KEEP(*(".irq_vector_table.*"))
*(.text)
*(".text.*")
__text_end = .;
} GROUP_LINK_IN(ROMABLE_REGION)
SECTION_PROLOGUE (devconfig, (OPTIONAL),)
{
__devconfig_start = .;
*(".devconfig.*")
KEEP(*(SORT_BY_NAME(".devconfig*")))
__devconfig_end = .;
} GROUP_LINK_IN(ROMABLE_REGION)
SECTION_PROLOGUE(_CTOR_SECTION_NAME,,) {
/*
* The compiler fills the constructor pointers table below, hence
* symbol __CTOR_LIST__ must be aligned on 4 byte boundary.
* To align with the C++ standard, the first element of the array
* contains the number of actual constructors. The last element is
* NULL.
*/
. = ALIGN(4);
__CTOR_LIST__ = .;
LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
KEEP(*(SORT_BY_NAME(".ctors*")))
LONG(0)
__CTOR_END__ = .;
} GROUP_LINK_IN(ROMABLE_REGION)
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) {
*(.rodata)
*(".rodata.*")
} GROUP_LINK_IN(ROMABLE_REGION)
__data_rom_start = ALIGN(4); /* XIP imaged DATA ROM start addr */
GROUP_END(ROMABLE_REGION)
GROUP_START(RAMABLE_REGION)
#if defined(CONFIG_XIP)
SECTION_AT_PROLOGUE(_DATA_SECTION_NAME,,,_DATA_IN_ROM) {
#else
SECTION_PROLOGUE(_DATA_SECTION_NAME,,) {
#endif
/* when XIP, .text is in ROM, but vector table must be at start of .data */
__data_ram_start = .;
*(.data)
*(".data.*")
} GROUP_LINK_IN(RAMABLE_REGION)
SECTION_PROLOGUE(initlevel, (OPTIONAL),)
{
__initconfig_start = .;
INIT_LEVEL(0)
INIT_LEVEL(1)
INIT_LEVEL(2)
INIT_LEVEL(3)
INIT_LEVEL(4)
INIT_LEVEL(5)
INIT_LEVEL(6)
INIT_LEVEL(7)
KEEP(*(SORT_BY_NAME(".initconfig*")))
__initconfig_end = .;
} GROUP_LINK_IN(RAMABLE_REGION)
__data_ram_end = .;
SECTION_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) {
/*
* For performance, BSS section is assumed to be 4 byte aligned and
* a multiple of 4 bytes
*/
. = ALIGN(4);
__bss_start = .;
*(.bss)
*(".bss.*")
COMMON_SYMBOLS
/*
* BSP clears this memory in words only and doesn't clear any
* potential left over bytes.
*/
__bss_end = ALIGN(4);
} GROUP_LINK_IN(RAMABLE_REGION)
SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),) {
/*
* This section is used for non-initialized objects that
* will not be cleared during the boot process.
*/
*(.noinit)
*(".noinit.*")
} GROUP_LINK_IN(RAMABLE_REGION)
/* Define linker symbols */
_end = .; /* end of image */
__bss_num_words = (__bss_end - __bss_start) >> 2;
GROUP_END(RAMABLE_REGION)
/* Data Closely Coupled Memory (DCCM) */
GROUP_START(DCCM)
GROUP_END(DCCM)
}
#ifdef CONFIG_XIP
/*
* Round up number of words for DATA section to ensure that XIP copies the
* entire data section. XIP copy is done in words only, so there may be up
* to 3 extra bytes copied in next section (BSS). At run time, the XIP copy
* is done first followed by clearing the BSS section.
*/
__data_size = (__data_ram_end - __data_ram_start);
__data_num_words = (__data_size + 3) >> 2;
#endif

67
arch/arc/platforms/generic/irq_vector_table.c Normal file
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@ -0,0 +1,67 @@
/* irq_vector_table.c - IRQ part of vector table for generic arc BSP */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
This file contains the IRQ part of the vector table. It is meant to be used
for one of two cases:
a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
binds _IsrWrapper() to all the IRQ entries in the vector table.
b) When the BSP is written so that device ISRs are installed directly in the
vector table, they are enumerated here.
*/
#include <toolchain.h>
#include <sections.h>
extern void _isr_enter(void);
typedef void (*vth)(void); /* Vector Table Handler */
#if defined(CONFIG_SW_ISR_TABLE)
vth __irq_vector_table _IrqVectorTable[CONFIG_NUM_IRQS] = {
[0 ...(CONFIG_NUM_IRQS - 1)] = _isr_enter
};
#elif !defined(CONFIG_IRQ_VECTOR_TABLE_CUSTOM)
extern void _SpuriousIRQ(void);
/* placeholders: fill with real ISRs */
vth __irq_vector_table _IrqVectorTable[CONFIG_NUM_IRQS] = {
[0 ...(CONFIG_NUM_IRQS - 1)] = _SpuriousIRQ
};
#endif /* CONFIG_SW_ISR_TABLE */

56
arch/arc/platforms/generic/linker.cmd Normal file
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@ -0,0 +1,56 @@
/* linker.cmd - Linker command/script file */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
This is the linker script for both standard images and XIP images.
*/
/* Flash base address and size */
#define FLASH_START 0x40034000 /* Flash bank 1 */
#define FLASH_SIZE 152K
/*
* SRAM base address and size
*
* Internal SRAM includes the exception vector table at reset, which is at
* the beginning of the region.
*/
#define SRAM_START CONFIG_RAM_START
#define SRAM_SIZE CONFIG_RAM_SIZE
/* Data Closely Coupled Memory (DCCM) base address and size */
#define DCCM_START 0x80000000
#define DCCM_SIZE 8K
#include "generic.cmd"

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/* sw_isr_table.c - Software ISR table for generic arc BSP */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
This contains the ISR table meant to be used for ISRs that take a parameter.
It is also used when ISRs are to be connected at runtime, and in this case
provides a table that is filled with _SpuriousIRQ bindings.
*/
#include <toolchain.h>
#include <sections.h>
#include <sw_isr_table.h>
extern void _irq_spurious(void *arg);
#if defined(CONFIG_SW_ISR_TABLE_DYNAMIC)
_IsrTableEntry_t __isr_table_section _sw_isr_table[CONFIG_NUM_IRQS] = {
[0 ...(CONFIG_NUM_IRQS - 1)].arg = (void *)0xABAD1DEA,
[0 ...(CONFIG_NUM_IRQS - 1)].isr = _irq_spurious
};
#else
#if defined(CONFIG_SW_ISR_TABLE)
#if !defined(CONFIG_SW_ISR_TABLE_STATIC_CUSTOM)
/* placeholders: fill with real ISRs */
_IsrTableEntry_t __isr_table_section _IsrTable[CONFIG_NUM_IRQS] = {
[0 ...(CONFIG_NUM_IRQS - 1)].arg = (void *)0xABAD1DEA,
[0 ...(CONFIG_NUM_IRQS - 1)].isr = _SpuriousIRQ
};
#endif
#endif
#endif

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/* system.c - system/hardware module for generic arc BSP */
/*
* Copyright (c) 2014-2015 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
This module provides routines to initialize and support board-level hardware
for the generic arc BSP.
*/
#include <nanokernel.h>
#include <board.h>
#include <init.h>
#include <drivers/uart.h>
/* Cannot use microkernel, since only nanokernel is supported */
#if defined(CONFIG_MICROKERNEL)
#error "Microkernel support is not available"
#endif
#if defined(CONFIG_PRINTK) || defined(CONFIG_STDOUT_CONSOLE)
#include <console/uart_console.h>
/**
*
* @brief initialize target-only console
*
* Only used for debugging, no host driver involved.
*
* RETURNS: N/A
*
*/
static void consoleInit(void)
{
struct uart_init_info info = {
.baud_rate = CONFIG_UART_CONSOLE_BAUDRATE,
.options = 0,
.sys_clk_freq = CONFIG_UART_CONSOLE_CLK_FREQ,
.regs = CONFIG_UART_CONSOLE_REGS,
.irq = CONFIG_UART_CONSOLE_IRQ,
.int_pri = CONFIG_UART_CONSOLE_INT_PRI,
};
uart_init(CONFIG_UART_CONSOLE_INDEX, &info);
uartConsoleInit();
}
#else
#define consoleInit() do { /* do nothing */ } while ((0))
#endif /* defined(CONFIG_PRINTK) || defined(CONFIG_STDOUT_CONSOLE) */
/**
*
* @brief perform basic hardware initialization
*
* Hardware initialized:
* - interrupt unit
* - serial port and console driver
*
* RETURNS: N/A
*/
static int generic_init(struct device *arg)
{
ARG_UNUSED(arg);
_arc_v2_irq_unit_init();
consoleInit(); /* NOP if not needed */
return 0;
}
DECLARE_DEVICE_INIT_CONFIG(generic_0, "", generic_init, NULL);
pure_early_init(generic_0, NULL);