zephyr/drivers/i2c/Kconfig.dw

57 lines
1.9 KiB
Text
Raw Permalink Normal View History

# Copyright (c) 2018 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
menuconfig I2C_DW
bool "Design Ware I2C support"
default y
depends on DT_HAS_SNPS_DESIGNWARE_I2C_ENABLED
select PINCTRL if $(dt_compat_any_has_prop,$(DT_COMPAT_SNPS_DESIGNWARE_I2C),pinctrl-0)
depends on !$(dt_compat_any_has_prop,$(DT_COMPAT_SNPS_DESIGNWARE_I2C),clocks) || CLOCK_CONTROL
select PCIE if $(dt_compat_on_bus,$(DT_COMPAT_SNPS_DESIGNWARE_I2C),pcie)
select DYNAMIC_INTERRUPTS if $(dt_compat_on_bus,$(DT_COMPAT_SNPS_DESIGNWARE_I2C),pcie)
select I2C_TRANSFER_TIMEOUT_SUPPORTED
help
Enable the Design Ware I2C driver
if I2C_DW
config I2C_DW_CLOCK_SPEED
int "Set the clock speed for I2C"
default 100 if I2C_RTS5912
default 32
config I2C_DW_LPSS_DMA
bool "Use I2C integrated DMA for asynchronous transfer"
depends on !I2C_RTS5912
select DMA
select DMA_INTEL_LPSS
help
This option enables I2C DMA feature to be used for asynchronous
data transfers. All Tx operations are done using dma channel 0 and
all Rx operations are done using dma channel 1.
config I2C_DW_EXTENDED_SUPPORT
bool "Extended DW features"
help
This option enables support for the SCL/SDA timeout registers and some
additional features of the DW I2C controller.
config I2C_DW_PM_POLICY_STATE_LOCK
bool "Lock power managemnet policy during I2C transfers"
help
Enable this option to block power management policy state changes
during I2C transfers.
config I2C_DW_IC_CLK_FREQ_OPTIMIZATION
bool "Core Clock Frequency Optimization"
help
Enable hardware optimization to reduce the required I2C core clock frequency.
This features reduces the internal latency cycles required to generate the
SCL high and low periods, allowing the controller to achieve target bus
speeds with a lower system clock frequency (ic_clk).
Enable this option only if your hardware IP supports this specific latency
reduction feature.
endif # I2C_DW