drivers: i2c: i2c_dw: Added intel lpss dma support for I2C
Enabled intel LPSS DMA interface using dw common to support usage of internal DMA in LPSS I2C to transfer and receive data. Signed-off-by: Bindu S <bindu.s@intel.com>
This commit is contained in:
Bindu S
Carles Cufí
parent
292ca93795
commit
877208dc78
4 changed files with 224 additions and 2 deletions
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@ -12,3 +12,12 @@ config I2C_DW_CLOCK_SPEED
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int "Set the clock speed for I2C"
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depends on I2C_DW
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default 32
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config I2C_DW_LPSS_DMA
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bool "Use I2C integrated DMA for asynchronous transfer"
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select DMA
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select DMA_INTEL_LPSS
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help
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This option enables I2C DMA feature to be used for asynchrounous
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data transfers. All Tx operaton are done using dma channel 0 and
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all Rx operations are done using dma channel 1.
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@ -30,6 +30,11 @@
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#include <zephyr/sys/util.h>
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#if defined(CONFIG_I2C_DW_LPSS_DMA)
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#include <zephyr/drivers/dma.h>
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#include <zephyr/drivers/dma/dma_intel_lpss.h>
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#endif
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#ifdef CONFIG_IOAPIC
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#include <zephyr/drivers/interrupt_controller/ioapic.h>
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#endif
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@ -48,6 +53,147 @@ static inline uint32_t get_regs(const struct device *dev)
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return (uint32_t)DEVICE_MMIO_GET(dev);
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}
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#ifdef CONFIG_I2C_DW_LPSS_DMA
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void i2c_dw_enable_idma(const struct device *dev, bool enable)
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{
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uint32_t reg;
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uint32_t reg_base = get_regs(dev);
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if (enable) {
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write_dma_cr(DW_IC_DMA_ENABLE, reg_base);
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reg = sys_read32(reg_base + DW_IC_REG_DMA_CR);
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} else {
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reg = read_dma_cr(reg_base);
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reg &= ~DW_IC_DMA_ENABLE;
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write_dma_cr(reg, reg_base);
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reg = sys_read32(reg_base + DW_IC_REG_DMA_CR);
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}
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}
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void cb_i2c_idma_transfer(const struct device *dma, void *user_data,
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uint32_t channel, int status)
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{
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const struct device *dev = (const struct device *)user_data;
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struct i2c_dw_dev_config *const dw = dev->data;
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dma_stop(dw->dma_dev, channel);
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i2c_dw_enable_idma(dev, false);
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if (status) {
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dw->xfr_status = true;
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} else {
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dw->xfr_status = false;
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}
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}
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void i2c_dw_set_fifo_th(const struct device *dev, uint8_t fifo_depth)
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{
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uint32_t reg_base = get_regs(dev);
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write_tdlr(fifo_depth, reg_base);
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write_rdlr(fifo_depth - 1, reg_base);
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}
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inline void *i2c_dw_dr_phy_addr(const struct device *dev)
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{
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struct i2c_dw_dev_config *const dw = dev->data;
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return (void *) (dw->phy_addr + DW_IC_REG_DATA_CMD);
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}
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int32_t i2c_dw_idma_rx_transfer(const struct device *dev)
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{
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struct i2c_dw_dev_config *const dw = dev->data;
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struct dma_config dma_cfg = { 0 };
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struct dma_block_config dma_block_cfg = { 0 };
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if (!device_is_ready(dw->dma_dev)) {
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LOG_DBG("DMA device is not ready");
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return -ENODEV;
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}
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dma_cfg.dma_slot = 1U;
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dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
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dma_cfg.source_data_size = 1U;
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dma_cfg.dest_data_size = 1U;
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dma_cfg.source_burst_length = 1U;
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dma_cfg.dest_burst_length = 1U;
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dma_cfg.dma_callback = cb_i2c_idma_transfer;
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dma_cfg.user_data = (void *)dev;
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dma_cfg.complete_callback_en = 0U;
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dma_cfg.error_callback_en = 1U;
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dma_cfg.block_count = 1U;
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dma_cfg.head_block = &dma_block_cfg;
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dma_block_cfg.block_size = dw->xfr_len;
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dma_block_cfg.dest_address = (uint64_t)&dw->xfr_buf[0];
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dma_block_cfg.source_address = (uint64_t)i2c_dw_dr_phy_addr(dev);
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dw->xfr_status = false;
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if (dma_config(dw->dma_dev, DMA_INTEL_LPSS_RX_CHAN, &dma_cfg)) {
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LOG_DBG("Error transfer");
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return -EIO;
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}
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if (dma_start(dw->dma_dev, DMA_INTEL_LPSS_RX_CHAN)) {
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LOG_DBG("Error transfer");
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return -EIO;
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}
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i2c_dw_enable_idma(dev, true);
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i2c_dw_set_fifo_th(dev, 1);
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return 0;
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}
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int32_t i2c_dw_idma_tx_transfer(const struct device *dev,
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uint64_t data)
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{
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struct i2c_dw_dev_config *const dw = dev->data;
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struct dma_config dma_cfg = { 0 };
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struct dma_block_config dma_block_cfg = { 0 };
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if (!device_is_ready(dw->dma_dev)) {
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LOG_DBG("DMA device is not ready");
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return -ENODEV;
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}
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dma_cfg.dma_slot = 0U;
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dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
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dma_cfg.source_data_size = 1U;
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dma_cfg.dest_data_size = 1U;
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dma_cfg.source_burst_length = 1U;
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dma_cfg.dest_burst_length = 1U;
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dma_cfg.dma_callback = cb_i2c_idma_transfer;
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dma_cfg.user_data = (void *)dev;
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dma_cfg.complete_callback_en = 0U;
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dma_cfg.error_callback_en = 1U;
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dma_cfg.block_count = 1U;
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dma_cfg.head_block = &dma_block_cfg;
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dma_block_cfg.block_size = 1;
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dma_block_cfg.source_address = (uint64_t)&data;
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dma_block_cfg.dest_address = (uint64_t)i2c_dw_dr_phy_addr(dev);
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dw->xfr_status = false;
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if (dma_config(dw->dma_dev, DMA_INTEL_LPSS_TX_CHAN, &dma_cfg)) {
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LOG_DBG("Error transfer");
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return -EIO;
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}
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if (dma_start(dw->dma_dev, DMA_INTEL_LPSS_TX_CHAN)) {
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LOG_DBG("Error trnasfer");
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return -EIO;
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}
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i2c_dw_enable_idma(dev, true);
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i2c_dw_set_fifo_th(dev, 1);
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return 0;
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}
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#endif
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static inline void i2c_dw_data_ask(const struct device *dev)
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{
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struct i2c_dw_dev_config * const dw = dev->data;
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@ -119,6 +265,13 @@ static void i2c_dw_data_read(const struct device *dev)
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struct i2c_dw_dev_config * const dw = dev->data;
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uint32_t reg_base = get_regs(dev);
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#ifdef CONFIG_I2C_DW_LPSS_DMA
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if (test_bit_status_rfne(reg_base) && (dw->xfr_len > 0)) {
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i2c_dw_idma_rx_transfer(dev);
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dw->xfr_len = 0;
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dw->rx_pending = 0;
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}
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#else
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while (test_bit_status_rfne(reg_base) && (dw->xfr_len > 0)) {
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dw->xfr_buf[0] = (uint8_t)read_cmd_data(reg_base);
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@ -130,7 +283,7 @@ static void i2c_dw_data_read(const struct device *dev)
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break;
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}
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}
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#endif
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/* Nothing to receive anymore */
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if (dw->xfr_len == 0U) {
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dw->state &= ~I2C_DW_CMD_RECV;
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@ -169,8 +322,11 @@ static int i2c_dw_data_send(const struct device *dev)
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data |= IC_DATA_CMD_STOP;
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}
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#ifdef CONFIG_I2C_DW_LPSS_DMA
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i2c_dw_idma_tx_transfer(dev, data);
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#else
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write_cmd_data(data, reg_base);
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#endif
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dw->xfr_len--;
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dw->xfr_buf++;
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@ -230,6 +386,16 @@ static void i2c_dw_isr(const struct device *port)
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/* Check if we are configured as a master device */
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if (test_bit_con_master_mode(reg_base)) {
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#ifdef CONFIG_I2C_DW_LPSS_DMA
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uint32_t stat = sys_read32(reg_base + IDMA_REG_INTR_STS);
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if (stat & IDMA_TX_RX_CHAN_MASK) {
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/* Handle the DMA interrupt */
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dma_intel_lpss_isr(dw->dma_dev);
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}
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#endif
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/* Bail early if there is any error. */
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if ((DW_INTR_STAT_TX_ABRT | DW_INTR_STAT_TX_OVER |
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DW_INTR_STAT_RX_OVER | DW_INTR_STAT_RX_UNDER) &
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@ -879,6 +1045,26 @@ static int i2c_dw_initialize(const struct device *dev)
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device_map(DEVICE_MMIO_RAM_PTR(dev), mbar.phys_addr,
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mbar.size, K_MEM_CACHE_NONE);
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pcie_set_cmd(rom->pcie->bdf, PCIE_CONF_CMDSTAT_MASTER, true);
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#ifdef CONFIG_I2C_DW_LPSS_DMA
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size_t nhdls = 0;
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const device_handle_t *hdls;
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hdls = device_supported_handles_get(dev, &nhdls);
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dw->dma_dev = device_from_handle(*hdls);
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/* Assign physical & virtual address to dma instance */
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dw->phy_addr = mbar.phys_addr;
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dw->base_addr = (uint32_t)(DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_OFFSET);
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sys_write32((uint32_t)dw->phy_addr,
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DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_REMAP_LOW);
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sys_write32((uint32_t)(dw->phy_addr >> DMA_INTEL_LPSS_ADDR_RIGHT_SHIFT),
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DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_REMAP_HI);
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LOG_DBG("i2c instance physical addr: [0x%lx], virtual addr: [0x%lx]",
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dw->phy_addr, dw->base_addr);
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#endif
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} else
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#endif
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{
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@ -889,6 +1075,7 @@ static int i2c_dw_initialize(const struct device *dev)
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k_mutex_init(&dw->bus_mutex);
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uint32_t reg_base = get_regs(dev);
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clear_bit_enable_en(reg_base);
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/* verify that we have a valid DesignWare register first */
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@ -123,6 +123,13 @@ struct i2c_dw_dev_config {
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uint8_t request_bytes;
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uint8_t xfr_flags;
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bool support_hs_mode;
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#ifdef CONFIG_I2C_DW_LPSS_DMA
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const struct device *dma_dev;
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uintptr_t phy_addr;
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uintptr_t base_addr;
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/* For dma transfer */
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bool xfr_status;
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#endif
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struct i2c_target_config *slave_cfg;
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};
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@ -144,14 +144,25 @@ union ic_comp_param_1_register {
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#define DW_IC_REG_STATUS (0x70)
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#define DW_IC_REG_TXFLR (0x74)
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#define DW_IC_REG_RXFLR (0x78)
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#define DW_IC_REG_DMA_CR (0x88)
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#define DW_IC_REG_TDLR (0x8C)
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#define DW_IC_REG_RDLR (0x90)
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#define DW_IC_REG_FS_SPKLEN (0xA0)
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#define DW_IC_REG_HS_SPKLEN (0xA4)
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#define DW_IC_REG_COMP_PARAM_1 (0xF4)
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#define DW_IC_REG_COMP_TYPE (0xFC)
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#define IDMA_REG_INTR_STS 0xAE8
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#define IDMA_TX_RX_CHAN_MASK 0x3
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/* CON Bit */
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#define DW_IC_CON_MASTER_MODE_BIT (0)
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/* DMA control bits */
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#define DW_IC_DMA_RX_ENABLE BIT(0)
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#define DW_IC_DMA_TX_ENABLE BIT(1)
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#define DW_IC_DMA_ENABLE (BIT(0) | BIT(1))
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DEFINE_TEST_BIT_OP(con_master_mode, DW_IC_REG_CON, DW_IC_CON_MASTER_MODE_BIT)
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DEFINE_MM_REG_WRITE(con, DW_IC_REG_CON, 32)
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DEFINE_MM_REG_READ(con, DW_IC_REG_CON, 32)
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@ -209,6 +220,14 @@ DEFINE_TEST_BIT_OP(status_rfne, DW_IC_REG_STATUS, DW_IC_STATUS_RFNE_BIT)
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DEFINE_MM_REG_READ(txflr, DW_IC_REG_TXFLR, 32)
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DEFINE_MM_REG_READ(rxflr, DW_IC_REG_RXFLR, 32)
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DEFINE_MM_REG_READ(dma_cr, DW_IC_REG_DMA_CR, 32)
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DEFINE_MM_REG_WRITE(dma_cr, DW_IC_REG_DMA_CR, 32)
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DEFINE_MM_REG_READ(tdlr, DW_IC_REG_TDLR, 32)
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DEFINE_MM_REG_WRITE(tdlr, DW_IC_REG_TDLR, 32)
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DEFINE_MM_REG_READ(rdlr, DW_IC_REG_RDLR, 32)
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DEFINE_MM_REG_WRITE(rdlr, DW_IC_REG_RDLR, 32)
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DEFINE_MM_REG_READ(fs_spklen, DW_IC_REG_FS_SPKLEN, 32)
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DEFINE_MM_REG_READ(hs_spklen, DW_IC_REG_HS_SPKLEN, 32)
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