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zephyr/arch/xtensa/include/offsets_short_arch.h

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Xtensa port: Added fields offset support for kernel and thread structures. Change-Id: I9cc44f60757a2f988e2a6341da9591a5e5f54561 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-20 20:55:41 +01:00
/*
arch/xtensa: General cleanup, remove dead code There was a bunch of dead historical cruft floating around in the arch/xtensa tree, left over from older code versions. It's time to do a cleanup pass. This is entirely refactoring and size optimization, no behavior changes on any in-tree devices should be present. Among the more notable changes: + xtensa_context.h offered an elaborate API to deal with a stack frame and context layout that we no longer use. + xtensa_rtos.h was entirely dead code + xtensa_timer.h was a parallel abstraction layer implementing in the architecture layer what we're already doing in our timer driver. + The architecture thread structs (_callee_saved and _thread_arch) aren't used by current code, and had dead fields that were removed. Unfortunately for standards compliance and C++ compatibility it's not possible to leave an empty struct here, so they have a single byte field. + xtensa_api.h was really just some interrupt management inlines used by irq.h, so fold that code into the outer header. + Remove the stale assembly offsets. This architecture doesn't use that facility. All told, more than a thousand lines have been removed. Not bad. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-02-13 10:32:42 -08:00
* Copyright (c) 2021 Intel Corporation
Xtensa port: Added fields offset support for kernel and thread structures. Change-Id: I9cc44f60757a2f988e2a6341da9591a5e5f54561 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-20 20:55:41 +01:00
* SPDX-License-Identifier: Apache-2.0
*/
xtensa: Enable userspace Userspace support for Xtensa architecture using Xtensa MMU. Some considerations: - Syscalls are not inline functions like in other architectures because some compiler issues when using multiple registers to pass parameters to the syscall. So here we have a function call so we can use registers as we need. - TLS is not supported by xcc in xtensa and reading PS register is a privileged instruction. So, we have to use threadptr to know if a thread is an user mode thread. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com> Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-12-14 00:35:36 -08:00
#ifndef ZEPHYR_ARCH_XTENSA_INCLUDE_OFFSETS_SHORT_ARCH_H_
#define ZEPHYR_ARCH_XTENSA_INCLUDE_OFFSETS_SHORT_ARCH_H_
#define _thread_offset_to_flags \
(___thread_t_arch_OFFSET + ___thread_arch_t_flags_OFFSET)
#ifdef CONFIG_USERSPACE
#define _thread_offset_to_psp \
(___thread_t_arch_OFFSET + ___thread_arch_t_psp_OFFSET)
xtensa: userspace: prevent potential privilege escalation When context switching and dealing with non-nested interrupts, the context to be restored are saved in the thread stack. When userspace is enabled, this means saving context into the user stacks for user threads. This allows PS values to be manipulated externally by setting PS.RING in the saved PS value to 0, resulting in granting kernel access privilege when the thread is restored. To prevent this, we store the PS value into the thread struct instead, where user threads cannot manipulate that. Note that nested interrupts and syscalls are not using the user stack but the interrupt stack and thread privileged stack respectively, where they are not accessible under user mode. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-07 14:49:26 -07:00
#define _thread_offset_to_return_ps \
(___thread_t_arch_OFFSET + ___thread_arch_t_return_ps_OFFSET)
xtensa: Enable userspace Userspace support for Xtensa architecture using Xtensa MMU. Some considerations: - Syscalls are not inline functions like in other architectures because some compiler issues when using multiple registers to pass parameters to the syscall. So here we have a function call so we can use registers as we need. - TLS is not supported by xcc in xtensa and reading PS register is a privileged instruction. So, we have to use threadptr to know if a thread is an user mode thread. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com> Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-12-14 00:35:36 -08:00
#define _thread_offset_to_ptables \
(___thread_t_arch_OFFSET + ___thread_arch_t_ptables_OFFSET)
xtensa: userspace: swap page tables via assembly code Since the necessary register values are now pre-computed and stored in the memory domain struct, we can use them directly in various assembly locations, thus replacing the function call to xtensa_swap_update_page_tables(). Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-04 13:44:40 -07:00
#define _thread_offset_to_mem_domain \
(___thread_t_mem_domain_info_OFFSET + ___mem_domain_info_t_mem_domain_OFFSET)
#define _k_mem_domain_offset_to_arch_reg_asid \
(__k_mem_domain_t_arch_OFFSET + __arch_mem_domain_t_reg_asid_OFFSET)
#define _k_mem_domain_offset_to_arch_reg_ptevaddr \
(__k_mem_domain_t_arch_OFFSET + __arch_mem_domain_t_reg_ptevaddr_OFFSET)
#define _k_mem_domain_offset_to_arch_reg_ptepin_as \
(__k_mem_domain_t_arch_OFFSET + __arch_mem_domain_t_reg_ptepin_as_OFFSET)
#define _k_mem_domain_offset_to_arch_reg_ptepin_at \
(__k_mem_domain_t_arch_OFFSET + __arch_mem_domain_t_reg_ptepin_at_OFFSET)
#define _k_mem_domain_offset_to_arch_reg_vecpin_as \
(__k_mem_domain_t_arch_OFFSET + __arch_mem_domain_t_reg_vecpin_as_OFFSET)
#define _k_mem_domain_offset_to_arch_reg_vecpin_at \
(__k_mem_domain_t_arch_OFFSET + __arch_mem_domain_t_reg_vecpin_at_OFFSET)
xtensa: Enable userspace Userspace support for Xtensa architecture using Xtensa MMU. Some considerations: - Syscalls are not inline functions like in other architectures because some compiler issues when using multiple registers to pass parameters to the syscall. So here we have a function call so we can use registers as we need. - TLS is not supported by xcc in xtensa and reading PS register is a privileged instruction. So, we have to use threadptr to know if a thread is an user mode thread. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com> Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-12-14 00:35:36 -08:00
#endif /* CONFIG_USERSPACE */
#endif /* ZEPHYR_ARCH_XTENSA_INCLUDE_OFFSETS_SHORT_ARCH_H_ */
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