2019-04-06 15:08:09 +02:00
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# SPDX-License-Identifier: Apache-2.0
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2017-10-27 15:43:34 +02:00
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zephyr_cc_option(-mlongcalls)
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2019-10-24 17:08:21 +02:00
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zephyr_library()
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zephyr_library_sources(
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cpu_idle.c
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fatal.c
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window_vectors.S
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2023-12-06 22:42:05 +01:00
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xtensa_asm2_util.S
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2019-11-19 11:32:32 +01:00
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irq_manage.c
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2023-12-06 22:55:06 +01:00
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thread.c
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2023-12-08 22:42:59 +01:00
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vector_handlers.c
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2019-10-24 17:08:21 +02:00
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)
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zephyr_library_sources_ifdef(CONFIG_XTENSA_USE_CORE_CRT1 crt1.S)
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zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
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2020-10-02 23:55:34 +02:00
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zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c)
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2021-01-07 07:11:11 +01:00
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zephyr_library_sources_ifdef(CONFIG_XTENSA_ENABLE_BACKTRACE xtensa_backtrace.c)
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zephyr_library_sources_ifdef(CONFIG_XTENSA_ENABLE_BACKTRACE debug_helpers_asm.S)
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2021-10-21 03:53:04 +02:00
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zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c)
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2022-06-06 16:49:27 +02:00
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zephyr_library_sources_ifdef(CONFIG_TIMING_FUNCTIONS timing.c)
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2021-10-26 21:58:21 +02:00
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zephyr_library_sources_ifdef(CONFIG_GDBSTUB gdbstub.c)
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2023-11-20 00:44:56 +01:00
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zephyr_library_sources_ifdef(CONFIG_XTENSA_MMU ptables.c mmu.c)
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2024-03-16 01:37:23 +01:00
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zephyr_library_sources_ifdef(CONFIG_XTENSA_MPU mpu.c)
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2024-01-27 00:10:47 +01:00
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zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S syscall_helper.c)
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2023-09-28 13:59:53 +02:00
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zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c)
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2023-12-08 19:09:31 +01:00
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zephyr_library_sources_ifdef(CONFIG_SMP smp.c)
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2024-01-10 21:58:32 +01:00
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zephyr_library_sources_ifdef(CONFIG_XTENSA_HIFI_SHARING xtensa_hifi.S)
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2021-10-26 21:58:21 +02:00
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2023-10-12 20:00:45 +02:00
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zephyr_library_sources_ifdef(
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CONFIG_KERNEL_VM_USE_CUSTOM_MEM_RANGE_CHECK
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mem_manage.c
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)
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2022-01-21 01:27:46 +01:00
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if("${ZEPHYR_TOOLCHAIN_VARIANT}" STREQUAL "xcc")
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zephyr_library_sources(xcc_stubs.c)
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endif()
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2017-10-27 15:43:34 +02:00
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add_subdirectory(startup)
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2022-01-09 00:51:04 +01:00
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# This produces a preprocessed and regenerated (in the sense of gcc
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# -dM, supported by all Xtensa toolchains) core-isa.h file available
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# as "core-isa-dM.h". This can be easily parsed by non-C tooling.
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#
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# Note that this adds the SOC/HAL include directory explicitly, they
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2022-01-20 20:11:08 +01:00
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# are the official places where we find core-isa.h. (Also that we
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# undefine __XCC_ because that compiler actually trips an error trying
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# to build this file to protect against mismatched versions.)
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2024-01-24 10:35:04 +01:00
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set(CORE_ISA_DM ${CMAKE_BINARY_DIR}/zephyr/include/generated/zephyr/core-isa-dM.h)
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2022-01-09 00:51:04 +01:00
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set(CORE_ISA_IN ${CMAKE_BINARY_DIR}/zephyr/include/generated/core-isa-dM.c)
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2022-01-20 20:11:08 +01:00
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file(WRITE ${CORE_ISA_IN} "#include <xtensa/config/core-isa.h>\n")
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2022-01-09 00:51:04 +01:00
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add_custom_command(OUTPUT ${CORE_ISA_DM}
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2022-01-20 20:11:08 +01:00
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COMMAND ${CMAKE_C_COMPILER} -E -dM -U__XCC__
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2022-01-09 00:51:04 +01:00
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-I${ZEPHYR_XTENSA_MODULE_DIR}/zephyr/soc/${CONFIG_SOC}
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2022-09-14 22:23:15 +02:00
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-I${SOC_FULL_DIR}
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2022-01-09 00:51:04 +01:00
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${CORE_ISA_IN} -o ${CORE_ISA_DM})
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2024-01-27 00:10:47 +01:00
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if(CONFIG_USERSPACE AND NOT CONFIG_THREAD_LOCAL_STORAGE)
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# It is possible that the SoC does not have THREADPTR.
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# This means that we cannot use THREADPTR as a shortcut to
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# in arch_is_user_context(). However, whether a SoC has
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# THREADPTR is in core-isa.h which can be parsed in gen_zsr.py.
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# There, if there is no THREADPTR, we need a scratch register
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# so we can do arch_is_user_context() via syscall.
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set(MAY_NEED_SYSCALL_SCRATCH_REG true)
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else()
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# With thread local storage, the variable is_user_mode is
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# stored in the thread's TLS area. There is no need for
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# scratch register.
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set(MAY_NEED_SYSCALL_SCRATCH_REG false)
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endif()
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2022-01-09 00:51:04 +01:00
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# Generates a list of device-specific scratch register choices
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2024-01-24 10:35:04 +01:00
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set(ZSR_H ${CMAKE_BINARY_DIR}/zephyr/include/generated/zephyr/zsr.h)
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2022-01-09 00:51:04 +01:00
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add_custom_command(OUTPUT ${ZSR_H} DEPENDS ${CORE_ISA_DM}
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COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/gen_zsr.py
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2023-02-16 20:25:48 +01:00
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$<$<BOOL:${CONFIG_XTENSA_MMU}>:--mmu>
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2024-01-27 00:10:47 +01:00
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$<$<BOOL:${MAY_NEED_SYSCALL_SCRATCH_REG}>:--syscall-scratch>
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2024-01-27 00:42:03 +01:00
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$<$<BOOL:${CONFIG_KERNEL_COHERENCE}>:--coherence>
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2022-01-09 00:51:04 +01:00
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${CORE_ISA_DM} ${ZSR_H})
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add_custom_target(zsr_h DEPENDS ${ZSR_H})
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add_dependencies(zephyr_interface zsr_h)
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2024-01-27 00:10:47 +01:00
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unset(MAY_NEED_SYSCALL_SCRATCH_REG)
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2023-07-31 17:34:28 +02:00
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# Similar: auto-generate interrupt handlers
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set(HANDLERS ${CMAKE_BINARY_DIR}/zephyr/include/generated/xtensa_handlers)
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add_custom_command(
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OUTPUT ${HANDLERS}_tmp.c
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COMMAND ${CMAKE_C_COMPILER} -E -U__XCC__
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-I${ZEPHYR_XTENSA_MODULE_DIR}/zephyr/soc/${CONFIG_SOC}
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-o ${HANDLERS}_tmp.c
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- < ${CMAKE_CURRENT_SOURCE_DIR}/xtensa_intgen.tmpl)
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add_custom_command(
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OUTPUT ${HANDLERS}.h
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DEPENDS ${HANDLERS}_tmp.c
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COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/xtensa_intgen.py
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${HANDLERS}_tmp.c > ${HANDLERS}.h)
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add_custom_target(xtensa_handlers_h DEPENDS ${HANDLERS}.h)
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add_dependencies(zephyr_interface xtensa_handlers_h)
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2023-07-31 21:32:45 +02:00
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# Auto-generate interrupt vector entry
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set(VECS_LD ${CMAKE_BINARY_DIR}/zephyr/include/generated/xtensa_vectors.ld)
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add_custom_command(OUTPUT ${VECS_LD} DEPENDS ${CORE_ISA_DM}
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COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/gen_vectors.py
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${CORE_ISA_DM} > ${VECS_LD})
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add_custom_target(xtensa_vectors_ld DEPENDS ${VECS_LD})
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add_dependencies(zephyr_interface xtensa_vectors_ld)
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