2015-04-11 01:44:37 +02:00
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/*
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2015-08-20 17:04:01 +02:00
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* Copyright (c) 2011-2015 Wind River Systems, Inc.
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2015-04-11 01:44:37 +02:00
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*
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2017-01-19 02:01:01 +01:00
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* SPDX-License-Identifier: Apache-2.0
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2015-04-11 01:44:37 +02:00
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*/
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2015-12-04 16:09:39 +01:00
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/**
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* @file
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* @brief Exception management support for IA-32 architecture
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*
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* This module implements assembly routines to manage exceptions (synchronous
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* interrupts) on the Intel IA-32 architecture. More specifically,
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* exceptions are implemented in this module. The stubs are invoked when entering
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* and exiting a C exception handler.
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2015-07-01 23:22:39 +02:00
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*/
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2015-04-11 01:44:37 +02:00
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2022-05-09 13:56:13 +02:00
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#include <zephyr/arch/x86/ia32/asm.h>
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#include <zephyr/arch/x86/ia32/arch.h> /* For MK_ISR_NAME */
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2016-11-08 16:36:50 +01:00
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#include <offsets_short.h>
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2015-04-11 01:44:37 +02:00
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/* exports (internal APIs) */
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2016-09-26 23:34:33 +02:00
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GTEXT(_exception_enter)
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2017-04-19 00:22:54 +02:00
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GTEXT(_kernel_oops_handler)
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2015-04-11 01:44:37 +02:00
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/* externs (internal APIs) */
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2019-12-18 23:12:54 +01:00
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GTEXT(z_x86_do_kernel_oops)
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2017-04-19 00:22:54 +02:00
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2015-07-01 23:22:39 +02:00
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/**
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*
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2015-07-01 23:51:40 +02:00
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* @brief Inform the kernel of an exception
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2015-07-01 23:22:39 +02:00
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*
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* This function is called from the exception stub created by nanoCpuExcConnect()
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* to inform the kernel of an exception. This routine currently does
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2015-08-20 17:04:01 +02:00
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* _not_ increment a thread/interrupt specific exception count. Also,
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2015-07-01 23:22:39 +02:00
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* execution of the exception handler occurs on the current stack, i.e.
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2016-09-26 23:34:33 +02:00
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* this does not switch to another stack. The volatile integer
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2015-07-01 23:22:39 +02:00
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* registers are saved on the stack, and control is returned back to the
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* exception stub.
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*
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* WARNINGS
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*
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* Host-based tools and the target-based GDB agent depend on the stack frame
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* created by this routine to determine the locations of volatile registers.
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* These tools must be updated to reflect any changes to the stack frame.
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*
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* C function prototype:
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*
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2020-05-27 18:26:57 +02:00
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* void _exception_enter(uint32_t error_code, void *handler)
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2015-07-01 23:22:39 +02:00
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*
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*/
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2015-04-11 01:44:37 +02:00
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2021-02-26 01:42:53 +01:00
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SECTION_FUNC(PINNED_TEXT, _exception_enter)
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2015-04-11 01:44:37 +02:00
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/*
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2016-08-02 00:59:10 +02:00
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* The gen_idt tool creates an interrupt-gate descriptor for
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2015-04-11 01:44:37 +02:00
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* all connections. The processor will automatically clear the IF
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* bit in the EFLAGS register upon execution of the handler, thus
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2016-09-26 23:34:33 +02:00
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* this does need not issue an 'cli' as the first instruction.
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*
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2015-04-11 01:44:37 +02:00
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* Note that the processor has pushed both the EFLAGS register
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* and the linear return address (cs:eip) onto the stack prior
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* to invoking the handler specified in the IDT.
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*
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* Clear the direction flag. It is automatically restored when the
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* exception exits.
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*/
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cld
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2019-02-07 00:35:24 +01:00
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#ifdef CONFIG_X86_KPTI
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call z_x86_trampoline_to_kernel
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#endif
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2015-04-11 01:44:37 +02:00
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/*
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2016-09-26 23:34:33 +02:00
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* Swap ecx and handler function on the current stack;
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2015-04-11 01:44:37 +02:00
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*/
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2016-01-15 01:22:28 +01:00
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xchgl %ecx, (%esp)
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2015-04-11 01:44:37 +02:00
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x86: remove dynamically generated IRQ and exception code
We are interested in supporting some XIP x86 platforms which are
unable to fetch CPU instructions from system RAM. This requires
refactoring our dynamic IRQ/exc code which currently synthesizes
assembly language instructions to create IRQ stubs on-the-fly.
Instead, a new approach is taken. Given that the configuration at
build time specifies the number of required stubs, use this
to generate a build time a set of tiny stub functions which simply
push a 'stub id' and then call common dynamic interrupt code.
The handler function and handler argument is saved in a table keyed by
this stub id.
CONFIG_EOI_HANDLER_SUPPORTED removed, the code hasn't been conditionally
compiled for some time and in all cases we call _loapic_eoi() when
finished with an interrupt.
Some other out-of-date verbiage in comments related to supporting
non-APIC removed.
Previously, when dynamic exceptions were created a pointer would
be passed in by the caller reserving ram for the stub code. Since
this is no longer feasible, two new Kconfig options have been added.
CONFIG_NUM_DYNAMIC_EXC_STUBS and CONFIG_NUM_DYNAMIC_EXC_NO_ERR_STUBS
control how many stubs are created for exceptions that push
an error code, and no error code, respectively.
SW Interrupts are no longer triggered by "int <vector>" hard-coded
assembly instructions. Instead this is done by sending a self-directed
inter-processor interrupt from the LOAPIC, using a new API
loapic_int_vect_trigger(). In this way we get rid of dynamically
generated code in irq_test_common.h.
All interrupts call _loapic_eoi() when finished, since this is now
the right thing to do for all IRQs, including SW interrupts.
_irq_handler_set() for x86 no longer requires the old function pointer
to be supplied.
Change-Id: I78993d3d00dd153c9051c518b417cce8d3acee9e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2015-10-19 23:10:53 +02:00
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/* By the time we get here, the stack should look like this:
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2016-01-15 01:22:28 +01:00
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* ESP -> ECX (excepting task)
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* Exception Error code (or junk)
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x86: remove dynamically generated IRQ and exception code
We are interested in supporting some XIP x86 platforms which are
unable to fetch CPU instructions from system RAM. This requires
refactoring our dynamic IRQ/exc code which currently synthesizes
assembly language instructions to create IRQ stubs on-the-fly.
Instead, a new approach is taken. Given that the configuration at
build time specifies the number of required stubs, use this
to generate a build time a set of tiny stub functions which simply
push a 'stub id' and then call common dynamic interrupt code.
The handler function and handler argument is saved in a table keyed by
this stub id.
CONFIG_EOI_HANDLER_SUPPORTED removed, the code hasn't been conditionally
compiled for some time and in all cases we call _loapic_eoi() when
finished with an interrupt.
Some other out-of-date verbiage in comments related to supporting
non-APIC removed.
Previously, when dynamic exceptions were created a pointer would
be passed in by the caller reserving ram for the stub code. Since
this is no longer feasible, two new Kconfig options have been added.
CONFIG_NUM_DYNAMIC_EXC_STUBS and CONFIG_NUM_DYNAMIC_EXC_NO_ERR_STUBS
control how many stubs are created for exceptions that push
an error code, and no error code, respectively.
SW Interrupts are no longer triggered by "int <vector>" hard-coded
assembly instructions. Instead this is done by sending a self-directed
inter-processor interrupt from the LOAPIC, using a new API
loapic_int_vect_trigger(). In this way we get rid of dynamically
generated code in irq_test_common.h.
All interrupts call _loapic_eoi() when finished, since this is now
the right thing to do for all IRQs, including SW interrupts.
_irq_handler_set() for x86 no longer requires the old function pointer
to be supplied.
Change-Id: I78993d3d00dd153c9051c518b417cce8d3acee9e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2015-10-19 23:10:53 +02:00
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* EIP (excepting task)
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* CS (excepting task)
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* EFLAGS (excepting task)
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* ...
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*
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2016-09-26 23:34:33 +02:00
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* ECX now contains the address of the handler function */
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x86: remove dynamically generated IRQ and exception code
We are interested in supporting some XIP x86 platforms which are
unable to fetch CPU instructions from system RAM. This requires
refactoring our dynamic IRQ/exc code which currently synthesizes
assembly language instructions to create IRQ stubs on-the-fly.
Instead, a new approach is taken. Given that the configuration at
build time specifies the number of required stubs, use this
to generate a build time a set of tiny stub functions which simply
push a 'stub id' and then call common dynamic interrupt code.
The handler function and handler argument is saved in a table keyed by
this stub id.
CONFIG_EOI_HANDLER_SUPPORTED removed, the code hasn't been conditionally
compiled for some time and in all cases we call _loapic_eoi() when
finished with an interrupt.
Some other out-of-date verbiage in comments related to supporting
non-APIC removed.
Previously, when dynamic exceptions were created a pointer would
be passed in by the caller reserving ram for the stub code. Since
this is no longer feasible, two new Kconfig options have been added.
CONFIG_NUM_DYNAMIC_EXC_STUBS and CONFIG_NUM_DYNAMIC_EXC_NO_ERR_STUBS
control how many stubs are created for exceptions that push
an error code, and no error code, respectively.
SW Interrupts are no longer triggered by "int <vector>" hard-coded
assembly instructions. Instead this is done by sending a self-directed
inter-processor interrupt from the LOAPIC, using a new API
loapic_int_vect_trigger(). In this way we get rid of dynamically
generated code in irq_test_common.h.
All interrupts call _loapic_eoi() when finished, since this is now
the right thing to do for all IRQs, including SW interrupts.
_irq_handler_set() for x86 no longer requires the old function pointer
to be supplied.
Change-Id: I78993d3d00dd153c9051c518b417cce8d3acee9e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2015-10-19 23:10:53 +02:00
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2015-04-11 01:44:37 +02:00
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/*
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* Push the remaining volatile registers on the existing stack.
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*/
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2016-01-15 01:22:28 +01:00
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pushl %eax
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2015-04-11 01:44:37 +02:00
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pushl %edx
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/*
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* Push the cooperative registers on the existing stack as they are
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* required by debug tools.
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*/
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pushl %edi
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pushl %esi
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pushl %ebx
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pushl %ebp
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2019-02-14 22:43:47 +01:00
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#ifdef CONFIG_USERSPACE
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/* Test if interrupted context was in ring 3 */
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testb $3, 36(%esp)
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jz 1f
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/* It was. The original stack pointer is on the stack 44 bytes
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* from the current top
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*/
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pushl 44(%esp)
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jmp 2f
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1:
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#endif
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2016-01-15 01:22:28 +01:00
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leal 44(%esp), %eax /* Calculate ESP before interrupt occurred */
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pushl %eax /* Save calculated ESP */
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2019-02-14 22:43:47 +01:00
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#ifdef CONFIG_USERSPACE
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2:
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2020-05-22 01:55:28 +02:00
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#endif
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#ifdef CONFIG_GDBSTUB
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pushl %ds
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pushl %es
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pushl %fs
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pushl %gs
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pushl %ss
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2019-02-14 22:43:47 +01:00
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#endif
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2015-04-11 01:44:37 +02:00
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/* ESP is pointing to the ESF at this point */
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2020-05-03 11:18:37 +02:00
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#if defined(CONFIG_LAZY_FPU_SHARING)
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2015-04-11 01:44:37 +02:00
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2016-11-08 16:36:50 +01:00
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movl _kernel + _kernel_offset_to_current, %edx
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2015-04-11 01:44:37 +02:00
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2016-11-08 16:36:50 +01:00
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/* inc exception nest count */
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incl _thread_offset_to_excNestCount(%edx)
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2015-04-11 01:44:37 +02:00
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/*
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2019-09-19 01:30:39 +02:00
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* Set X86_THREAD_FLAG_EXC in the current thread. This enables
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* z_swap() to preserve the thread's FP registers (where needed)
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* if the exception handler causes a context switch. It also
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* indicates to debug tools that an exception is being handled
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* in the event of a context switch.
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2015-04-11 01:44:37 +02:00
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*/
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2019-09-19 01:30:39 +02:00
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orb $X86_THREAD_FLAG_EXC, _thread_offset_to_flags(%edx)
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2015-04-11 01:44:37 +02:00
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2020-05-03 11:18:37 +02:00
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#endif /* CONFIG_LAZY_FPU_SHARING */
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2015-04-11 01:44:37 +02:00
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/*
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2016-09-26 23:34:33 +02:00
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* restore interrupt enable state, then call the handler
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2015-04-11 01:44:37 +02:00
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*
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* interrupts are enabled only if they were allowed at the time
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* the exception was triggered -- this protects kernel level code
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* that mustn't be interrupted
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*
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* Test IF bit of saved EFLAGS and re-enable interrupts if IF=1.
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*/
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/* ESP is still pointing to the ESF at this point */
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2019-07-17 00:21:19 +02:00
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testl $0x200, __z_arch_esf_t_eflags_OFFSET(%esp)
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2015-04-11 01:44:37 +02:00
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je allDone
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sti
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2016-08-18 18:25:00 +02:00
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allDone:
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2019-07-17 00:21:19 +02:00
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pushl %esp /* push z_arch_esf_t * parameter */
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2019-12-19 00:11:59 +01:00
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call *%ecx /* call exception handler */
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2016-09-26 23:34:33 +02:00
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addl $0x4, %esp
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2015-04-11 01:44:37 +02:00
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2020-05-03 11:18:37 +02:00
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#if defined(CONFIG_LAZY_FPU_SHARING)
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2015-04-11 01:44:37 +02:00
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2016-11-08 16:36:50 +01:00
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movl _kernel + _kernel_offset_to_current, %ecx
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2015-04-11 01:44:37 +02:00
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/*
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* Must lock interrupts to prevent outside interference.
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* (Using "lock" prefix would be nicer, but this won't work
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2015-07-27 18:19:36 +02:00
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* on platforms that don't respect the CPU's bus lock signal.)
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2015-04-11 01:44:37 +02:00
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*/
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cli
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/*
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* Determine whether exiting from a nested interrupt.
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*/
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2016-11-08 16:36:50 +01:00
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decl _thread_offset_to_excNestCount(%ecx)
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2015-04-11 01:44:37 +02:00
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2016-11-08 16:36:50 +01:00
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cmpl $0, _thread_offset_to_excNestCount(%ecx)
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2015-04-11 01:44:37 +02:00
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jne nestedException
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/*
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2019-09-19 01:30:39 +02:00
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* Clear X86_THREAD_FLAG_EXC in the k_thread of the current execution
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2016-11-08 16:36:50 +01:00
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* context if we are not in a nested exception (ie, when we exit the
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* outermost exception).
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2015-04-11 01:44:37 +02:00
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*/
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2019-09-19 01:30:39 +02:00
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andb $~X86_THREAD_FLAG_EXC, _thread_offset_to_flags(%ecx)
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2015-04-11 01:44:37 +02:00
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2016-08-18 18:25:00 +02:00
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nestedException:
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2020-05-03 11:18:37 +02:00
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#endif /* CONFIG_LAZY_FPU_SHARING */
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2015-04-11 01:44:37 +02:00
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2020-05-22 01:55:28 +02:00
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#ifdef CONFIG_GDBSTUB
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popl %ss
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popl %gs
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popl %fs
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popl %es
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popl %ds
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#endif
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2015-04-11 01:44:37 +02:00
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/*
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* Pop the non-volatile registers from the stack.
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* Note that debug tools may have altered the saved register values while
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* the task was stopped, and we want to pick up the altered values.
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*/
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2015-10-05 16:48:46 +02:00
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popl %ebp /* Discard saved ESP */
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2015-04-11 01:44:37 +02:00
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popl %ebp
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popl %ebx
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popl %esi
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popl %edi
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/* restore edx and ecx which are always saved on the stack */
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popl %edx
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popl %eax
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2016-01-15 01:22:28 +01:00
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popl %ecx
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2015-04-11 01:44:37 +02:00
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addl $4, %esp /* "pop" error code */
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/* Pop of EFLAGS will re-enable interrupts and restore direction flag */
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2019-02-07 00:35:24 +01:00
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KPTI_IRET
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2015-04-11 01:44:37 +02:00
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2021-02-26 01:42:53 +01:00
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SECTION_FUNC(PINNED_TEXT, _kernel_oops_handler)
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2017-04-19 00:22:54 +02:00
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push $0 /* dummy error code */
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2019-12-18 23:12:54 +01:00
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push $z_x86_do_kernel_oops
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2017-04-19 00:22:54 +02:00
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jmp _exception_enter
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