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zephyr/arch/common/Kconfig

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arch: common: dedicated `SEMIHOST` symbol Control the usage of semihosting with a dedicated symbol, instead of implying semihosting from the usage of `SEMIHOST_CONSOLE`. This allows semihosting to be used without the semihost console. Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2022-03-30 09:51:54 +02:00
# Common architecture configuration options
# Copyright (c) 2022, CSIRO.
# SPDX-License-Identifier: Apache-2.0
config SEMIHOST
bool "Semihosting support for ARM and RISC-V targets"
depends on ARM || ARM64 || RISCV
help
Semihosting is a mechanism that enables code running on an ARM or
RISC-V target to communicate and use the Input/Output facilities on
a host computer that is running a debugger.
Additional information can be found in:
https://developer.arm.com/documentation/dui0471/m/what-is-semihosting-
https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
This option is compatible with hardware and with QEMU, through the
(automatic) use of the -semihosting-config switch when invoking it.
arch: sw_isr: revamp multi-level interrupt architecture Previously the multi-level irq lookup table is generated by looping through the devicetree nodes using macros & Kconfig, which is hard to read and flimsy. This PR shifts the heavy lifting to devicetree & DT macros such that an interrupt controller driver, which has its info in the devicetree, can register itself directly with the multi-level interrupt architecture, which is more straightforward. The previous auto-generated look up table with macros is now moved in a file of its own. A new compatibility Kconfig: `CONFIG_LEGACY_MULTI_LEVEL_TABLE_GENERATION` is added and enabled by default to compile the legacy look up table for interrupt controller drivers that aren't updated to support the new architecture yet. Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-12-20 14:06:14 +01:00
config LEGACY_MULTI_LEVEL_TABLE_GENERATION
bool "Auto generates the multi-level interrupt LUT (deprecated)"
default y
select DEPRECATED
depends on MULTI_LEVEL_INTERRUPTS
depends on !PLIC
drivers: interrupt_controller: irq_steer: use new multilevel irq impl Update the NXP's irq_steer driver to use the new multi-level interrupt implementation. Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-02-02 06:13:06 +01:00
depends on !NXP_IRQSTEER
drivers: intc: update to use multi-level API Update these multi-level interrupt drivers to use the new API. Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-02-20 05:07:54 +01:00
depends on !RV32M1_INTMUX
depends on !CAVS_ICTL
depends on !DW_ICTL_ACE
depends on !DW_ICTL
arch: sw_isr: revamp multi-level interrupt architecture Previously the multi-level irq lookup table is generated by looping through the devicetree nodes using macros & Kconfig, which is hard to read and flimsy. This PR shifts the heavy lifting to devicetree & DT macros such that an interrupt controller driver, which has its info in the devicetree, can register itself directly with the multi-level interrupt architecture, which is more straightforward. The previous auto-generated look up table with macros is now moved in a file of its own. A new compatibility Kconfig: `CONFIG_LEGACY_MULTI_LEVEL_TABLE_GENERATION` is added and enabled by default to compile the legacy look up table for interrupt controller drivers that aren't updated to support the new architecture yet. Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-12-20 14:06:14 +01:00
help
A make-shift Kconfig to continue generating the multi-level interrupt LUT
with the legacy way using DT macros.
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