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zephyr/arch/arm/core/zimage_header.ld

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arch: arm: aarch32: Add ability to generate zImage header The image header is compatible for zImage(32) protocol. Offset Value Description 0x24 0x016F2818 Magic number to identify ARM Linux zImage 0x28 start address The address the zImage starts at 0x2C end address The address the zImage ends at As Zephyr can be built with a fixed load address, Xen/Uboot can read the image header and decide where to copy the Zephyr image. Also, it is to be noted that for AArch32 A/R, the vector table should be aligned to 0x20 address. Refer ARM DDI 0487I.a ID081822, G8-9815, G8.2.168, VBAR, Vector Base Address Register :- Bits[4:0] = RES0. For AArch32 M (Refer DDI0553B.v ID16122022, D1.2.269, VTOR, Vector Table Offset Register), Bits [6:0] = RES0. As zImage header occupies 0x30 bytes, thus it is necessary to align the vector table base address to 0x80 (which satisfies both VBAR and VTOR requirements). Also, it is to be noted that not all the AArch32 M class have VTOR, thus ARM_ZIMAGE_HEADER header depends on CPU_AARCH32_CORTEX_R || CPU_AARCH32_CORTEX_A || CPU_CORTEX_M_HAS_VTOR. The reason being the processors which does not have VBAR or VTOR, needs to have exception vector table at a fixed address in the beginning of ROM (Refer the comment in arch/arm/core/aarch32/cortex_m/CMakeLists.txt) . They cannot support any headers. Also, the first instruction in zImage header is to branch to the kernel start address. This is to support booting in situations where the zImage header need not be parsed. In case of Arm v8M, the first two entries in the reset vector should be "Initial value for the main stack pointer on reset" and "Start address for the reset handler" (Refer Armv8M DDI0553B.vID16122022, B3.30, Vector tables). In case of Armv7M (ARM DDI 0403E. ID021621, B1.5.3 The vector table), the first entry is "SP_main. This is the reset value of the Main stack pointer.". Thus when v7M or v8M starts from reset, it expects to see these values at the default reset vector location. See the following text from Armv7M (ARM DDI 0403E. ID021621, B1-526) "On powerup or reset, the processor uses the entry at offset 0 as the initial value for SP_main..." Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
2022-12-14 12:46:53 +00:00
/*
* Copyright (c) 2023, Advanced Micro Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#if defined(CONFIG_ARM_ZIMAGE_HEADER)
KEEP(*(.image_header))
KEEP(*(.".image_header.*"))
__end = .;
#endif
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