arm: soc: Add SoC series for ARM's Cortex-M Prototyping System (MPS2)
ARM's Cortex-M Prototyping System (or MPS2) [1] is a board containing
devices such as RAM, ethernet and display, and at its heart there is an
FPGA which can be programmed with various 'SoCs' which implement the
CPU, SRAM, UARTs, SPI, DMA, etc. There are also software simulations of
systems based on this hardware which are part of ARM's Fixed Virtual
Platforms (FVPs).
All of the above could be regarded SoCs in the same series so we will
treat them as such in Zephyr.
In this initial patch we add SoC support for the public FPGA image
which implements a Cortex-M3 CPU, and includes definitions to support
use of the UARTs on this.
ARM's documentation for MPS2 images are titled 'Application Note ANnnn'
where the number nnn is different for each 'SoC'. E.g. Application Note
AN385 is for "ARM Cortex-M3 SMM on V2M-MPS2" [2]. The files ARM supply
for programming the board firmware also make extensive use of the ANnnn
nomenclature, so we will use this for the SoC name in Zephyr. E.g. the
Cortex-M3 SoC will be called 'mps2_an385'. Note, it is not possible to
use the CPU type (e.g. M3) for the name as there are multiple FPGA
images for some CPU types (e.g. there are three Cortex M7 images
with differing FPU and MPU support).
[1] https://www.arm.com/products/tools/development-boards/versatile-express/cortex-m-prototyping-system.php
[2] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0385c/index.html
Change-Id: Ice54f2d2cde7669582337f256c878526139daedd
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-01-04 15:18:34 +01:00
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/*
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* Copyright (c) 2017 Linaro Limited
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*
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2022-09-14 22:23:15 +02:00
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* Initial contents based on soc/soc_legacy/arm/ti_lm3s6965/soc.c which is:
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arm: soc: Add SoC series for ARM's Cortex-M Prototyping System (MPS2)
ARM's Cortex-M Prototyping System (or MPS2) [1] is a board containing
devices such as RAM, ethernet and display, and at its heart there is an
FPGA which can be programmed with various 'SoCs' which implement the
CPU, SRAM, UARTs, SPI, DMA, etc. There are also software simulations of
systems based on this hardware which are part of ARM's Fixed Virtual
Platforms (FVPs).
All of the above could be regarded SoCs in the same series so we will
treat them as such in Zephyr.
In this initial patch we add SoC support for the public FPGA image
which implements a Cortex-M3 CPU, and includes definitions to support
use of the UARTs on this.
ARM's documentation for MPS2 images are titled 'Application Note ANnnn'
where the number nnn is different for each 'SoC'. E.g. Application Note
AN385 is for "ARM Cortex-M3 SMM on V2M-MPS2" [2]. The files ARM supply
for programming the board firmware also make extensive use of the ANnnn
nomenclature, so we will use this for the SoC name in Zephyr. E.g. the
Cortex-M3 SoC will be called 'mps2_an385'. Note, it is not possible to
use the CPU type (e.g. M3) for the name as there are multiple FPGA
images for some CPU types (e.g. there are three Cortex M7 images
with differing FPU and MPU support).
[1] https://www.arm.com/products/tools/development-boards/versatile-express/cortex-m-prototyping-system.php
[2] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0385c/index.html
Change-Id: Ice54f2d2cde7669582337f256c878526139daedd
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-01-04 15:18:34 +01:00
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* Copyright (c) 2013-2015 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2022-05-06 11:11:04 +02:00
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#include <zephyr/drivers/gpio/gpio_mmio32.h>
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2017-01-06 14:59:03 +01:00
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#include <soc.h>
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2022-05-06 11:11:04 +02:00
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#include <zephyr/linker/linker-defs.h>
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2017-01-06 14:59:03 +01:00
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2020-04-23 08:14:06 +02:00
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2017-01-06 14:59:03 +01:00
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/* Setup GPIO drivers for accessing FPGAIO registers */
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2020-04-23 08:14:06 +02:00
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#define FPGAIO_NODE(n) DT_INST(n, arm_mps2_fpgaio_gpio)
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#define FPGAIO_INIT(n) \
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2021-04-09 14:45:54 +02:00
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GPIO_MMIO32_INIT(FPGAIO_NODE(n), \
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2020-04-23 08:14:06 +02:00
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DT_REG_ADDR(FPGAIO_NODE(n)), \
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BIT_MASK(DT_PROP(FPGAIO_NODE(n), ngpios)))
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/* We expect there to be 3 arm,mps2-fpgaio-gpio devices:
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* led0, button, and misc
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*/
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FPGAIO_INIT(0);
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FPGAIO_INIT(1);
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FPGAIO_INIT(2);
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arm: soc: Add SoC series for ARM's Cortex-M Prototyping System (MPS2)
ARM's Cortex-M Prototyping System (or MPS2) [1] is a board containing
devices such as RAM, ethernet and display, and at its heart there is an
FPGA which can be programmed with various 'SoCs' which implement the
CPU, SRAM, UARTs, SPI, DMA, etc. There are also software simulations of
systems based on this hardware which are part of ARM's Fixed Virtual
Platforms (FVPs).
All of the above could be regarded SoCs in the same series so we will
treat them as such in Zephyr.
In this initial patch we add SoC support for the public FPGA image
which implements a Cortex-M3 CPU, and includes definitions to support
use of the UARTs on this.
ARM's documentation for MPS2 images are titled 'Application Note ANnnn'
where the number nnn is different for each 'SoC'. E.g. Application Note
AN385 is for "ARM Cortex-M3 SMM on V2M-MPS2" [2]. The files ARM supply
for programming the board firmware also make extensive use of the ANnnn
nomenclature, so we will use this for the SoC name in Zephyr. E.g. the
Cortex-M3 SoC will be called 'mps2_an385'. Note, it is not possible to
use the CPU type (e.g. M3) for the name as there are multiple FPGA
images for some CPU types (e.g. there are three Cortex M7 images
with differing FPU and MPU support).
[1] https://www.arm.com/products/tools/development-boards/versatile-express/cortex-m-prototyping-system.php
[2] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0385c/index.html
Change-Id: Ice54f2d2cde7669582337f256c878526139daedd
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-01-04 15:18:34 +01:00
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2019-05-06 10:56:38 +02:00
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/* (Secure System Control) Base Address */
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#define SSE_200_SYSTEM_CTRL_S_BASE (0x50021000UL)
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#define SSE_200_SYSTEM_CTRL_INITSVTOR1 (SSE_200_SYSTEM_CTRL_S_BASE + 0x114)
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#define SSE_200_SYSTEM_CTRL_CPU_WAIT (SSE_200_SYSTEM_CTRL_S_BASE + 0x118)
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#define SSE_200_CPU_ID_UNIT_BASE (0x5001F000UL)
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2019-07-03 13:48:05 +02:00
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/* The base address that the application image will start at on the secondary
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* (non-TrustZone) Cortex-M33 mcu.
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*/
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2022-11-08 09:14:29 +01:00
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#define CPU1_FLASH_ADDRESS (0x38B000)
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2019-07-03 13:48:05 +02:00
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/* The memory map offset for the application image, which is used
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* to determine the location of the reset vector at startup.
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*/
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#define CPU1_FLASH_OFFSET (0x10000000)
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2019-05-06 10:56:38 +02:00
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/**
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2022-03-16 22:07:43 +01:00
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* @brief Wake up CPU 1 from another CPU, this is platform specific.
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2019-05-06 10:56:38 +02:00
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*/
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void wakeup_cpu1(void)
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{
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/* Set the Initial Secure Reset Vector Register for CPU 1 */
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2020-05-27 18:26:57 +02:00
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*(uint32_t *)(SSE_200_SYSTEM_CTRL_INITSVTOR1) =
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2020-09-21 14:52:22 +02:00
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(uint32_t)_vector_start +
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2019-07-03 13:48:05 +02:00
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CPU1_FLASH_ADDRESS -
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CPU1_FLASH_OFFSET;
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2019-05-06 10:56:38 +02:00
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/* Set the CPU Boot wait control after reset */
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2020-05-27 18:26:57 +02:00
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*(uint32_t *)(SSE_200_SYSTEM_CTRL_CPU_WAIT) = 0;
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2019-05-06 10:56:38 +02:00
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}
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/**
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2022-03-16 22:07:43 +01:00
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* @brief Get the current CPU ID, this is platform specific.
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2019-05-06 10:56:38 +02:00
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*
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* @return Current CPU ID
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*/
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2020-05-27 18:26:57 +02:00
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uint32_t sse_200_platform_get_cpu_id(void)
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2019-05-06 10:56:38 +02:00
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{
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2020-05-27 18:26:57 +02:00
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volatile uint32_t *p_cpu_id = (volatile uint32_t *)SSE_200_CPU_ID_UNIT_BASE;
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2019-05-06 10:56:38 +02:00
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2020-05-27 18:26:57 +02:00
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return (uint32_t)*p_cpu_id;
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2019-05-06 10:56:38 +02:00
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}
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