arm: soc: Add SoC series for ARM's Cortex-M Prototyping System (MPS2)

ARM's Cortex-M Prototyping System (or MPS2) [1] is a board containing
devices such as RAM, ethernet and display, and at its heart there is an
FPGA which can be programmed with various 'SoCs' which implement the
CPU, SRAM, UARTs, SPI, DMA, etc. There are also software simulations of
systems based on this hardware which are part of ARM's Fixed Virtual
Platforms (FVPs).

All of the above could be regarded SoCs in the same series so we will
treat them as such in Zephyr.

In this initial patch we add SoC support for the public FPGA image
which implements a Cortex-M3 CPU, and includes definitions to support
use of the UARTs on this.

ARM's documentation for MPS2 images are titled 'Application Note ANnnn'
where the number nnn is different for each 'SoC'. E.g. Application Note
AN385 is for "ARM Cortex-M3 SMM on V2M-MPS2" [2]. The files ARM supply
for programming the board firmware also make extensive use of the ANnnn
nomenclature, so we will use this for the SoC name in Zephyr. E.g. the
Cortex-M3 SoC will be called 'mps2_an385'. Note, it is not possible to
use the CPU type (e.g. M3) for the name as there are multiple FPGA
images for some CPU types (e.g. there are three Cortex M7 images
with differing FPU and MPU support).

[1] https://www.arm.com/products/tools/development-boards/versatile-express/cortex-m-prototyping-system.php
[2] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0385c/index.html

Change-Id: Ice54f2d2cde7669582337f256c878526139daedd
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This commit is contained in:
Jon Medhurst 2017-01-04 14:18:34 +00:00 committed by Kumar Gala
commit cd8fd42de9
12 changed files with 229 additions and 0 deletions

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@ -313,6 +313,12 @@ M: Maureen Helm <maureen.helm@nxp.com>
S: Supported
F: ext/hal/nxp/mcux/
MPS2 - ARM LTD CORTEX-M PROTOTYPING SYSTEM
M: Jon Medhurst (Tixy) <tixy@linaro.org>
M: Vincenzo Frascino <vincenzo.frascino@linaro.org>
S: Supported
F: arch/arm/soc/arm/mps2/
NETWORKING
M: Jukka Rissanen <jukka.rissanen@linux.intel.com>
M: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>

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@ -0,0 +1,16 @@
#
# Copyright (c) 2017 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_MPS2_AN385
config SOC
default mps2_an385
config NUM_IRQS
int
default 32
endif

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@ -0,0 +1,34 @@
#
# Copyright (c) 2017 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_SERIES_MPS2
config SOC_SERIES
default mps2
config NUM_IRQ_PRIO_BITS
int
default 3
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 25000000
config SRAM_BASE_ADDRESS
default 0x20000000
config SRAM_SIZE
default 4096
config FLASH_BASE_ADDRESS
default 0x00000000
config FLASH_SIZE
default 4096
source "arch/arm/soc/arm/mps2/Kconfig.defconfig.mps2*"
endif # SOC_SERIES_MPS2

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@ -0,0 +1,14 @@
#
# Copyright (c) 2017 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#
config SOC_SERIES_MPS2
bool "ARM MPS2 MCU Series"
depends on ARM
select SOC_FAMILY_ARM
select CPU_CORTEX_M
select CPU_HAS_SYSTICK
help
Enable support for ARM MPS2 MCU Series

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@ -0,0 +1,15 @@
#
# Copyright (c) 2017 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#
choice
prompt "ARM MPS2 SoCs"
depends on SOC_SERIES_MPS2
config SOC_MPS2_AN385
bool "ARM Cortex-M3 SMM on V2M-MPS2 (Application Note AN385)"
select CPU_CORTEX_M3
endchoice

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@ -0,0 +1,7 @@
#
# Copyright (c) 2017 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#
obj-y += soc.o

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@ -0,0 +1,9 @@
/* linker.ld - Linker command/script file */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arch/arm/cortex_m/scripts/linker.ld>

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@ -0,0 +1,31 @@
/*
* Copyright (c) 2017 Linaro Limited
*
* Initial contents based on arch/arm/soc/ti_lm3s6965/soc.c which is:
* Copyright (c) 2013-2015 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arch/cpu.h>
#include <init.h>
/**
* @brief Perform basic hardware initialization at boot.
*
* @return 0
*/
static int arm_mps2_init(struct device *arg)
{
ARG_UNUSED(arg);
/*
* Install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
return 0;
}
SYS_INIT(arm_mps2_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

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@ -0,0 +1,12 @@
/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_H_
#define _SOC_H_
#include <soc_devices.h>
#endif /* _SOC_H_ */

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@ -0,0 +1,31 @@
/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_DEVICES_H_
#define _SOC_DEVICES_H_
#include <soc_memory_map.h>
#include <soc_irq.h>
#if defined(CONFIG_UART_CMSDK_APB)
#define CMSDK_APB_UART0 UART_0_BASE_ADDR
#define CMSDK_APB_UART_0_IRQ_TX IRQ_UART_0_TX
#define CMSDK_APB_UART_0_IRQ_RX IRQ_UART_0_RX
#define CMSDK_APB_UART1 UART_1_BASE_ADDR
#define CMSDK_APB_UART_1_IRQ_TX IRQ_UART_1_TX
#define CMSDK_APB_UART_1_IRQ_RX IRQ_UART_1_RX
#define CMSDK_APB_UART2 UART_2_BASE_ADDR
#define CMSDK_APB_UART_2_IRQ_TX IRQ_UART_2_TX
#define CMSDK_APB_UART_2_IRQ_RX IRQ_UART_2_RX
#define CMSDK_APB_UART3 UART_3_BASE_ADDR
#define CMSDK_APB_UART_3_IRQ_TX IRQ_UART_3_TX
#define CMSDK_APB_UART_3_IRQ_RX IRQ_UART_3_RX
#define CMSDK_APB_UART4 UART_4_BASE_ADDR
#define CMSDK_APB_UART_4_IRQ_TX IRQ_UART_4_TX
#define CMSDK_APB_UART_4_IRQ_RX IRQ_UART_4_RX
#endif
#endif /* _SOC_DEVICES_H_ */

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@ -0,0 +1,38 @@
/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_IRQ_H_
#define _SOC_IRQ_H_
#define IRQ_UART_0_RX 0
#define IRQ_UART_0_TX 1
#define IRQ_UART_1_RX 2
#define IRQ_UART_1_TX 3
#define IRQ_UART_2_RX 4
#define IRQ_UART_2_TX 5
#define IRQ_GPIO_0_COMBINED 6
#define IRQ_GPIO_1_COMBINED 7
#define IRQ_TIMER_0 8
#define IRQ_TIMER_1 9
#define IRQ_DUAL_TIMER 10
#define IRQ_SPI_1 11
#define IRQ_UART_0_OVERFLOW 12
#define IRQ_UART_1_OVERFLOW 12
#define IRQ_UART_2_OVERFLOW 12
#define IRQ_ETHERNET 13
#define IRQ_AUDIO_I2S 14
#define IRQ_TOUCHSCREEN 15
#define IRQ_GPIO_2_COMBINED 16
#define IRQ_GPIO_3_COMBINED 17
#define IRQ_UART_3_RX 18
#define IRQ_UART_3_TX 19
#define IRQ_UART_4_RX 20
#define IRQ_UART_4_TX 21
#define IRQ_SPI_2 22
#define IRQ_SPI_3 23
#define IRQ_GPIO_0 24
#endif /* _SOC_IRQ_H_ */

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@ -0,0 +1,16 @@
/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_MEMORY_MAP_H_
#define _SOC_MEMORY_MAP_H_
#define UART_0_BASE_ADDR 0x40004000
#define UART_1_BASE_ADDR 0x40005000
#define UART_2_BASE_ADDR 0x40006000
#define UART_3_BASE_ADDR 0x40007000
#define UART_4_BASE_ADDR 0x40009000
#endif /* _SOC_MEMORY_MAP_H_ */