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334aea068c
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ch81: add a LICENSE and README
/ core (push) Successful in 5m37s
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2026-05-14 12:13:31 +02:00 |
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ad52989831
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ch81: fix up gendispatch after missing some AI rewrites
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2026-05-08 20:43:13 +02:00 |
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6da25f8da4
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WIP: tailcall
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2026-04-20 17:00:04 +02:00 |
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9d4ec9499f
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WIP: attributes for tail call
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2026-04-20 16:03:34 +02:00 |
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47d5ba861f
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ch81: let the most common instructions bypass _next
/ core (push) Successful in 5m12s
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2026-04-19 19:40:29 +02:00 |
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1d1095d542
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ch81: move PC to a local variable
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2026-04-19 16:18:23 +02:00 |
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b2dcbcbbec
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ch81: collapse the IX, IY support into one
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2026-04-19 16:00:29 +02:00 |
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f6c6e46d79
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ch81: drop the unused code from gendispatch
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2026-04-18 15:59:27 +02:00 |
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3c080b36dd
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ch81: support compressing the bit/set/res opcodes
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2026-04-18 15:38:49 +02:00 |
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b819314310
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ch81: reduce the Zephyr RAM usage
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2026-04-18 14:35:32 +02:00 |
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a452204431
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ch81: move Board to an interface
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2026-04-12 20:37:25 +02:00 |
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849be245aa
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ch81: begin tidying up the cores
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2026-04-12 19:40:36 +02:00 |
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370ed264f4
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ch81: move regs.a to a local variable
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2026-04-12 16:13:16 +02:00 |
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a7f09fb8a4
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ch81: make an implicit A explicit and move A to a parameter
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2026-04-12 15:47:19 +02:00 |
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c4d710fcf5
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ch81: support trapping literal jumps
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2026-04-12 11:57:17 +02:00 |
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51e3e6c5ce
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ch81: implement many of the undocumented opcodes
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2026-04-11 14:35:51 +02:00 |
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139e773c3e
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ch81: make z80test run to completion
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2026-04-11 13:30:25 +02:00 |
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42a07e1df4
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ch81: move the ZX81 specific code out and fix bugs found by z80test
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2026-04-11 11:31:51 +02:00 |
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6e1baf3358
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ch81: move to a opcode-table.json based dispatch
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2026-04-04 19:38:19 +02:00 |
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bf07377409
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ch81: parse the opcode-table and expand
|
2026-04-04 08:36:44 +02:00 |
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65e5c3d909
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ch81: split asm.py into the parser and generator
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2026-04-03 13:26:31 +02:00 |
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978c51f7b8
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ch81: call board_ directly rather than using indirect
|
2026-04-03 13:14:36 +02:00 |
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6d67dbb767
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ch81: continue making the code more idiomatic
|
2026-04-03 11:19:58 +02:00 |
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b70fc30bca
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ch81: tidy up by de-macroing and deduplicating
|
2026-04-03 11:06:41 +02:00 |
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5b800e222c
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ch81: split the implementation out of the class
|
2026-04-03 10:39:07 +02:00 |
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288af06580
|
ch81: as Emu is templated, move the implementation into the header
|
2026-04-03 10:24:36 +02:00 |
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7f0bea0aef
|
ch81: fix the remaining instructions
|
2026-04-02 20:26:26 +02:00 |
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9db784f600
|
ch81: support bytecode tables
|
2026-04-02 20:08:03 +02:00 |
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314b1cc6c5
|
ch81: added jump targets and interrupt handling
|
2026-04-02 18:01:57 +02:00 |
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2c961bc37b
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ch81: enough so that it hits the first display render
|
2026-04-02 15:27:58 +02:00 |
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78198d943b
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ch81: implement a first set of instructions
|
2026-04-02 15:02:51 +02:00 |
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515620a974
|
ch81: split af into separate fields. Add the return address to call
|
2026-04-02 15:02:36 +02:00 |
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8fd43ab880
|
ch81: switch to bit flags from an enum
|
2026-04-02 13:06:56 +02:00 |
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052e23a50f
|
ch81: implement the register file
|
2026-03-29 21:47:43 +02:00 |
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9e45cbfbe6
|
ch81: reduce the number of labels
|
2026-03-29 20:43:30 +02:00 |
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daf82e971d
|
ch81: add a lst parser and wire in return addresses
|
2026-03-29 19:53:07 +02:00 |
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2eacd89f95
|
ch81: add a open81.asm parser
|
2026-03-29 16:10:23 +02:00 |
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2088877346
|
ch81: tidy up the board into a class, split functions out, and make the ROM const
|
2026-03-12 19:57:34 +01:00 |
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51c5b045c5
|
ch81: move out of tools and make it build from scratch
|
2025-08-01 15:52:31 +02:00 |
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6acb0e514a
|
ch81: passes through self test
continuous-integration/drone/push Build is failing
|
2025-07-26 13:32:06 +00:00 |
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a62d9c22a8
|
ch81: fix ADD/SUB for other registers; add a Ld16
|
2025-07-26 13:31:49 +00:00 |
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c5f17f9762
|
ch81: create a tool to diff two runs
|
2025-07-26 13:30:27 +00:00 |
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|
9ef1afbb2a
|
ch81: bump before reinstalling
|
2025-07-21 18:01:21 +00:00 |
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32a94179eb
|
ch81: implement nop, ld, and add
|
2025-07-16 17:02:19 +00:00 |
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60d616d9b6
|
ch81: added the left and right fetchers and fixed condition codes
|
2025-07-16 14:42:41 +00:00 |
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|
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9ef1dab1a2
|
ch81: tidied up the table rendering
|
2025-07-16 12:11:18 +00:00 |
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|
|
4c9b027f77
|
ch81: rename instruction to opcode to match the datasheet
|
2025-07-16 12:00:32 +00:00 |
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|
28ee259464
|
ch81: pull the two-operand form out of genz80
|
2025-07-16 11:43:40 +00:00 |
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|
fcacd7f902
|
ch81: split expansion out from rendering
|
2025-07-16 11:23:54 +00:00 |
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|
|
36450fbaa0
|
ch81: split genz80 into functional areas
|
2025-07-14 18:02:40 +00:00 |
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