ef8200dfcd
Precursor patches have arranged that conditional compilation hanging on CONFIG_CPU_CORTEX_M3_M4 provides support for ARMv7-M, rename the config variable to reflect this. Change-Id: Ifa56e3c1c04505d061b2af3aec9d8b9e55b5853d Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
124 lines
3.2 KiB
ArmAsm
124 lines
3.2 KiB
ArmAsm
/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief Fault handlers for ARM Cortex-M
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*
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* Fault handlers for ARM Cortex-M processors.
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*/
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#define _ASMLANGUAGE
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#include <toolchain.h>
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#include <sections.h>
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#include <arch/cpu.h>
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_ASM_FILE_PROLOGUE
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GTEXT(_Fault)
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GTEXT(__hard_fault)
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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GTEXT(__mpu_fault)
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GTEXT(__bus_fault)
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GTEXT(__usage_fault)
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GTEXT(__debug_monitor)
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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GTEXT(__reserved)
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/**
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*
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* @brief Fault handler installed in the fault and reserved vectors
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*
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* Entry point for the hard fault, MPU fault, bus fault, usage fault, debug
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* monitor and reserved exceptions.
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*
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* Save the values of the MSP and PSP in r0 and r1 respectively, so the first
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* and second parameters to the _Fault() C function that will handle the rest.
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* This has to be done because at this point we do not know if the fault
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* happened while handling an exception or not, and thus the ESF could be on
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* either stack. _Fault() will find out where the ESF resides.
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*
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* Provides these symbols:
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*
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* __hard_fault
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* __mpu_fault
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* __bus_fault
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* __usage_fault
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* __debug_monitor
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* __reserved
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*/
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SECTION_SUBSEC_FUNC(TEXT,__fault,__hard_fault)
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__mpu_fault)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__bus_fault)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__usage_fault)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__debug_monitor)
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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SECTION_SUBSEC_FUNC(TEXT,__fault,__reserved)
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#if defined(CONFIG_ARMV6_M)
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/* force unlock interrupts */
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cpsie i
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/* Use EXC_RETURN state to find out if stack frame is on the
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* MSP or PSP
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*/
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ldr r0, =0x4
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mov r1, lr
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tst r1, r0
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beq _stack_frame_msp
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mrs r0, PSP
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bne _stack_frame_endif
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_stack_frame_msp:
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mrs r0, MSP
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_stack_frame_endif:
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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/* force unlock interrupts */
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eors.n r0, r0
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msr BASEPRI, r0
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/* this reimplements _ScbIsNestedExc() */
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ldr ip, =_SCS_ICSR
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ldr ip, [ip]
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ands.w ip, #_SCS_ICSR_RETTOBASE
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ite eq /* is the RETTOBASE bit zero ? */
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mrseq r0, MSP /* if so, we're not returning to thread mode,
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* thus this is a nested exception: the stack
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* frame is on the MSP */
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mrsne r0, PSP /* if not, we are returning to thread mode, thus
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* this is not a nested exception: the stack
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* frame is on the PSP */
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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push {lr}
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bl _Fault
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pop {pc}
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.end
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