e671d363b8
This commit adds a new driver category for memory controller peripherals. There is no API involved for now, as it has not been found necessary for first implementation. STM32 Flexible Memory Controller (FMC) is the only controller supported for now. This peripheral allows to access multiple types of external memories, e.g. SDRAM, NAND, NOR Flash... The initial implementation adds support for the SDRAM controller only. The HAL API is used, so the implementation should be portable to other STM32 series. It has only been tested on H7 series, so for now it can only be enabled when working on H7. Linker facilities have also been added in order to allow applications to easily define a variable in SDRAM. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
49 lines
1.5 KiB
C
49 lines
1.5 KiB
C
/*
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* Copyright (c) 2020 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SDRAM_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SDRAM_H_
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/* Number of column address bits */
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#define STM32_FMC_SDRAM_NC_8 0x00000000UL
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#define STM32_FMC_SDRAM_NC_9 0x00000001UL
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#define STM32_FMC_SDRAM_NC_10 0x00000002UL
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#define STM32_FMC_SDRAM_NC_11 0x00000003UL
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/* Number of row address bits */
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#define STM32_FMC_SDRAM_NR_11 0x00000000UL
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#define STM32_FMC_SDRAM_NR_12 0x00000004UL
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#define STM32_FMC_SDRAM_NR_13 0x00000008UL
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/* Memory data bus width. */
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#define STM32_FMC_SDRAM_MWID_8 0x00000000UL
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#define STM32_FMC_SDRAM_MWID_16 0x00000010UL
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#define STM32_FMC_SDRAM_MWID_32 0x00000020UL
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/* Number of internal banks */
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#define STM32_FMC_SDRAM_NB_2 0x00000000UL
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#define STM32_FMC_SDRAM_NB_4 0x00000040UL
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/* CAS Latency */
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#define STM32_FMC_SDRAM_CAS_1 0x00000080UL
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#define STM32_FMC_SDRAM_CAS_2 0x00000100UL
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#define STM32_FMC_SDRAM_CAS_3 0x00000180UL
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/* SDRAM clock configuration */
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#define STM32_FMC_SDRAM_SDCLK_DISABLE 0x00000000UL
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#define STM32_FMC_SDRAM_SDCLK_PERIOD_2 0x00000800UL
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#define STM32_FMC_SDRAM_SDCLK_PERIOD_3 0x00000C00UL
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/* Burst read */
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#define STM32_FMC_SDRAM_RBURST_DISABLE 0x00000000UL
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#define STM32_FMC_SDRAM_RBURST_ENABLE 0x00001000UL
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/* Read pipe */
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#define STM32_FMC_SDRAM_RPIPE_0 0x00000000UL
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#define STM32_FMC_SDRAM_RPIPE_1 0x00002000UL
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#define STM32_FMC_SDRAM_RPIPE_2 0x00004000UL
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#endif
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