Andrew Boie e34f1cee06 x86: implement kernel page table isolation ... Implement a set of per-cpu trampoline stacks which all interrupts and exceptions will initially land on, and also as an intermediate stack for privilege changes as we need some stack space to swap page tables. Set up the special trampoline page which contains all the trampoline stacks, TSS, and GDT. This page needs to be present in the user page tables or interrupts don't work. CPU exceptions, with KPTI turned on, are treated as interrupts and not traps so that we have IRQs locked on exception entry. Add some additional macros for defining IDT entries. Add special handling of locore text/rodata sections when creating user mode page tables on x86-64. Restore qemu_x86_64 to use KPTI, and remove restrictions on enabling user mode on x86-64. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>		2020-01-17 16:17:39 -05:00
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core	x86: implement kernel page table isolation	2020-01-17 16:17:39 -05:00
include	x86: implement kernel page table isolation	2020-01-17 16:17:39 -05:00
CMakeLists.txt	x86: consolidate x86_64 architecture, SoC and boards	2019-10-25 17:57:55 -04:00
gen_gdt.py	scripts: Simplify code with sys.exit(<string>)	2019-09-08 12:34:16 +02:00
gen_idt.py	x86: gen_idt.py: Use enumerate() to fix pylint warning	2019-09-10 15:53:49 +02:00
ia32.cmake	arch/x86: remove support for IAMCU ABI	2019-09-07 10:07:42 -04:00
intel64.cmake	arch/x86: initial Intel64 bootstrap framework	2019-09-15 11:33:47 +08:00
Kconfig	x86: implement kernel page table isolation	2020-01-17 16:17:39 -05:00