zephyr/arch
Andrew Boie e34f1cee06 x86: implement kernel page table isolation
Implement a set of per-cpu trampoline stacks which all
interrupts and exceptions will initially land on, and also
as an intermediate stack for privilege changes as we need
some stack space to swap page tables.

Set up the special trampoline page which contains all the
trampoline stacks, TSS, and GDT. This page needs to be
present in the user page tables or interrupts don't work.

CPU exceptions, with KPTI turned on, are treated as interrupts
and not traps so that we have IRQs locked on exception entry.

Add some additional macros for defining IDT entries.

Add special handling of locore text/rodata sections when
creating user mode page tables on x86-64.

Restore qemu_x86_64 to use KPTI, and remove restrictions on
enabling user mode on x86-64.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-01-17 16:17:39 -05:00
..
arc kernel: cleanup and formally define CPU start fn 2020-01-13 16:35:10 -05:00
arm arch: arm: Rewrite Cortex-R reset vector function. 2020-01-10 10:34:17 +01:00
common arch: arm: Move ARM code to AArch32 sub-directory 2019-12-20 11:40:59 -05:00
nios2 global: Remove leading/trailing blank lines in files 2019-12-11 19:17:27 +01:00
posix POSIX arch: Fix C++ main() linkage issue 2019-12-18 21:53:47 +01:00
riscv riscv: use standard MSTATUS 2020-01-06 13:27:45 -05:00
x86 x86: implement kernel page table isolation 2020-01-17 16:17:39 -05:00
xtensa xtensa: fix atomic_cas reporting value swapped even when not 2020-01-08 19:57:05 -05:00
CMakeLists.txt arch: Simplify private header include path configuration. 2019-11-06 16:07:32 -08:00
Kconfig arch: arm: Rewrite Cortex-R reset vector function. 2020-01-10 10:34:17 +01:00