d95b7c4e64
Depending on the PLL, all DIV-P / DIV-Q and DIV-R are available on STM32MP13 PLLs. Adjust valid range in order to be able to set for all 4 PLLs. Clarify DT properties description. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
87 lines
2.3 KiB
YAML
87 lines
2.3 KiB
YAML
# Copyright (c) 2025 STMicroelectronics
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# SPDX-License-Identifier: Apache-2.0
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description: |
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PLL node binding for STM32MP13 devices
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It can be used to describe 4 different PLLs: PLL1, PLL2, PLL3 and PLL4.
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These PLLs can take one of hse_ck, hsi_ck or csi_ck as input clock.
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PLLM factor is used to set the input clock in this acceptable range.
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Each PLL has one output clock whose frequency can be computed with the
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following formula:
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f(PLL_P) = f(VCO clock) / (DIVP × DIVR × DIVQ)
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with f(VCO clock) = f(PLL clock input) × 2 × (((DIVN + 1) + (FRACV / 8192)) / DIVM1)
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Note: To reduce the power consumption, it is recommended to configure the VCOx
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clock output to the lowest frequency.
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The PLL1 output frequency must not exceed 2000 MHz.
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The PLL2 output frequency must not exceed 1600 MHz.
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The PLL3 output frequency must not exceed 800 MHz.
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The PLL4 output frequency must not exceed 800 MHz.
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Note: The CPU clock should not exceed 1Ghz so avoid configuring the PLL1 to more
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than 1000 MHz or program the mpuss_ck mux to use the MPUDIV
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(refer to the stm32mp13 reference manual for details)
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div-m (aka DIVM1 + 1), div-p (aka DIVP + 1), div-q (aka DIVQ + 1),
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div-r (aka DIVR + 1) have identical valid ranges for all 4 PLLs.
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mul-n (aka DIVN + 1) valid range depends on the PLL
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PLL1: 31 - 125
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PLL2: 25 - 100
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PLL3: 25 - 200
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PLL4: 25 - 200
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compatible: "st,stm32mp13-pll-clock"
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include: [clock-controller.yaml, base.yaml]
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properties:
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"#clock-cells":
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const: 0
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clocks:
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required: true
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div-m:
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type: int
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required: true
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description: |
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PLLx division factor (aka DIVM1 + 1) of the input clock divider
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Valid range: 1 - 64
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mul-n:
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type: int
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required: true
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description: |
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PLLx multiplication factor (aka DIVN + 1) for VCO
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Valid range: 25 - 200
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div-p:
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type: int
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description: |
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PLLx_P division factor (aka DIVP + 1)
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Valid range: 1 - 128
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div-q:
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type: int
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description: |
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PLLx_Q division factor (aka DIVQ + 1)
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Valid range: 1 - 128
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div-r:
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type: int
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description: |
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PLLx_R division factor (aka DIVR + 1)
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Valid range: 1 - 128
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frac-v:
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type: int
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description: |
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PLLx FRACV fractional latch
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Valid range: 1 - 8192
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