cc334c7273
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types. This handles the remaining includes and kernel, plus
touching up various points that we skipped because of include
dependancies. We also convert the PRI printf formatters in the arch
code over to normal formatters.
Jira: ZEP-2051
Change-Id: Iecbb12601a3ee4ea936fd7ddea37788a645b08b0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
489 lines
8.8 KiB
C
489 lines
8.8 KiB
C
/* Intel x86 GCC specific public inline assembler functions and macros */
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/*
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* Copyright (c) 2015, Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Either public functions or macros or invoked by public functions */
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#ifndef _ASM_INLINE_GCC_PUBLIC_GCC_H
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#define _ASM_INLINE_GCC_PUBLIC_GCC_H
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/*
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* The file must not be included directly
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* Include kernel.h instead
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*/
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#include <sys_io.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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#include <zephyr/types.h>
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#include <stddef.h>
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/**
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*
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* @internal
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*
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* @brief Disable all interrupts on the CPU
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*
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* GCC assembly internals of irq_lock(). See irq_lock() for a complete
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* description.
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*
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* @return An architecture-dependent lock-out key representing the
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* "interrupt disable state" prior to the call.
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*/
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static ALWAYS_INLINE unsigned int _do_irq_lock(void)
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{
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unsigned int key;
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__asm__ volatile (
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"pushfl;\n\t"
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"cli;\n\t"
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"popl %0;\n\t"
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: "=g" (key)
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:
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: "memory"
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);
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return key;
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}
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/**
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*
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* @internal
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*
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* @brief Enable all interrupts on the CPU (inline)
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*
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* GCC assembly internals of irq_lock_unlock(). See irq_lock_unlock() for a
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* complete description.
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*
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* @return N/A
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*/
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static ALWAYS_INLINE void _do_irq_unlock(void)
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{
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__asm__ volatile (
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"sti;\n\t"
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: : : "memory"
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);
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}
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/**
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*
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* @brief find least significant bit set in a 32-bit word
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*
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* This routine finds the first bit set starting from the least significant bit
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* in the argument passed in and returns the index of that bit. Bits are
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* numbered starting at 1 from the least significant bit. A return value of
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* zero indicates that the value passed is zero.
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*
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* @return least significant bit set, 0 if @a op is 0
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*
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* @internal
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* For Intel64 (x86_64) architectures, the 'cmovzl' can be removed and leverage
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* the fact that the 'bsfl' doesn't modify the destination operand when the
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* source operand is zero. The "bitpos" variable can be preloaded into the
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* destination register, and given the unconditional ++bitpos that is performed
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* after the 'cmovzl', the correct results are yielded.
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*/
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static ALWAYS_INLINE unsigned int find_lsb_set(u32_t op)
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{
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unsigned int bitpos;
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__asm__ volatile (
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#if defined(CONFIG_CMOV)
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"bsfl %1, %0;\n\t"
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"cmovzl %2, %0;\n\t"
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: "=r" (bitpos)
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: "rm" (op), "r" (-1)
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: "cc"
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#else
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"bsfl %1, %0;\n\t"
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"jnz 1f;\n\t"
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"movl $-1, %0;\n\t"
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"1:\n\t"
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: "=r" (bitpos)
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: "rm" (op)
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: "cc"
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#endif /* CONFIG_CMOV */
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);
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return (bitpos + 1);
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}
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/**
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*
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* @brief find most significant bit set in a 32-bit word
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*
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* This routine finds the first bit set starting from the most significant bit
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* in the argument passed in and returns the index of that bit. Bits are
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* numbered starting at 1 from the least significant bit. A return value of
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* zero indicates that the value passed is zero.
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*
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* @return most significant bit set, 0 if @a op is 0
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*
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* @internal
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* For Intel64 (x86_64) architectures, the 'cmovzl' can be removed and leverage
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* the fact that the 'bsfl' doesn't modify the destination operand when the
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* source operand is zero. The "bitpos" variable can be preloaded into the
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* destination register, and given the unconditional ++bitpos that is performed
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* after the 'cmovzl', the correct results are yielded.
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*/
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static ALWAYS_INLINE unsigned int find_msb_set(u32_t op)
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{
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unsigned int bitpos;
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__asm__ volatile (
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#if defined(CONFIG_CMOV)
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"bsrl %1, %0;\n\t"
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"cmovzl %2, %0;\n\t"
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: "=r" (bitpos)
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: "rm" (op), "r" (-1)
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#else
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"bsrl %1, %0;\n\t"
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"jnz 1f;\n\t"
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"movl $-1, %0;\n\t"
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"1:\n\t"
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: "=r" (bitpos)
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: "rm" (op)
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: "cc"
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#endif /* CONFIG_CMOV */
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);
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return (bitpos + 1);
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}
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/**
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* @brief read timestamp register ensuring serialization
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*/
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static inline u64_t _tsc_read(void)
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{
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union {
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struct {
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u32_t lo;
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u32_t hi;
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};
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u64_t value;
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} rv;
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/* rdtsc & cpuid clobbers eax, ebx, ecx and edx registers */
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__asm__ volatile (/* serialize */
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"xorl %%eax,%%eax;\n\t"
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"cpuid;\n\t"
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:
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:
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: "%eax", "%ebx", "%ecx", "%edx"
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);
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/*
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* We cannot use "=A", since this would use %rax on x86_64 and
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* return only the lower 32bits of the TSC
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*/
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__asm__ volatile ("rdtsc" : "=a" (rv.lo), "=d" (rv.hi));
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return rv.value;
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}
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/**
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*
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* @brief Get a 32 bit CPU timestamp counter
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*
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* @return a 32-bit number
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*/
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static ALWAYS_INLINE
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u32_t _do_read_cpu_timestamp32(void)
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{
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u32_t rv;
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__asm__ volatile("rdtsc" : "=a"(rv) : : "%edx");
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return rv;
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}
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/* Implementation of sys_io.h's documented functions */
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static ALWAYS_INLINE
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void sys_out8(u8_t data, io_port_t port)
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{
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__asm__ volatile("outb %b0, %w1;\n\t"
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:
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: "a"(data), "Nd"(port));
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}
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static ALWAYS_INLINE
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u8_t sys_in8(io_port_t port)
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{
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u8_t ret;
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__asm__ volatile("inb %w1, %b0;\n\t"
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: "=a"(ret)
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: "Nd"(port));
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return ret;
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}
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static ALWAYS_INLINE
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void sys_out16(u16_t data, io_port_t port)
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{
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__asm__ volatile("outw %w0, %w1;\n\t"
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:
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: "a"(data), "Nd"(port));
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}
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static ALWAYS_INLINE
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u16_t sys_in16(io_port_t port)
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{
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u16_t ret;
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__asm__ volatile("inw %w1, %w0;\n\t"
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: "=a"(ret)
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: "Nd"(port));
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return ret;
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}
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static ALWAYS_INLINE
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void sys_out32(u32_t data, io_port_t port)
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{
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__asm__ volatile("outl %0, %w1;\n\t"
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:
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: "a"(data), "Nd"(port));
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}
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static ALWAYS_INLINE
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u32_t sys_in32(io_port_t port)
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{
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u32_t ret;
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__asm__ volatile("inl %w1, %0;\n\t"
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: "=a"(ret)
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: "Nd"(port));
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return ret;
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}
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static ALWAYS_INLINE
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void sys_io_set_bit(io_port_t port, unsigned int bit)
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{
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u32_t reg = 0;
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__asm__ volatile("inl %w1, %0;\n\t"
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"btsl %2, %0;\n\t"
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"outl %0, %w1;\n\t"
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:
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: "a" (reg), "Nd" (port), "Ir" (bit));
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}
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static ALWAYS_INLINE
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void sys_io_clear_bit(io_port_t port, unsigned int bit)
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{
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u32_t reg = 0;
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__asm__ volatile("inl %w1, %0;\n\t"
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"btrl %2, %0;\n\t"
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"outl %0, %w1;\n\t"
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:
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: "a" (reg), "Nd" (port), "Ir" (bit));
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}
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static ALWAYS_INLINE
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int sys_io_test_bit(io_port_t port, unsigned int bit)
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{
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u32_t ret;
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__asm__ volatile("inl %w1, %0\n\t"
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"btl %2, %0\n\t"
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: "=a" (ret)
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: "Nd" (port), "Ir" (bit));
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return (ret & 1);
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}
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static ALWAYS_INLINE
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int sys_io_test_and_set_bit(io_port_t port, unsigned int bit)
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{
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int ret;
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ret = sys_io_test_bit(port, bit);
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sys_io_set_bit(port, bit);
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return ret;
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}
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static ALWAYS_INLINE
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int sys_io_test_and_clear_bit(io_port_t port, unsigned int bit)
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{
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int ret;
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ret = sys_io_test_bit(port, bit);
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sys_io_clear_bit(port, bit);
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return ret;
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}
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static ALWAYS_INLINE
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void sys_write8(u8_t data, mm_reg_t addr)
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{
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__asm__ volatile("movb %0, %1;\n\t"
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:
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: "q"(data), "m" (*(volatile u8_t *) addr)
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: "memory");
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}
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static ALWAYS_INLINE
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u8_t sys_read8(mm_reg_t addr)
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{
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u8_t ret;
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__asm__ volatile("movb %1, %0;\n\t"
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: "=q"(ret)
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: "m" (*(volatile u8_t *) addr)
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: "memory");
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return ret;
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}
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static ALWAYS_INLINE
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void sys_write16(u16_t data, mm_reg_t addr)
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{
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__asm__ volatile("movw %0, %1;\n\t"
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:
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: "r"(data), "m" (*(volatile u16_t *) addr)
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: "memory");
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}
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static ALWAYS_INLINE
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u16_t sys_read16(mm_reg_t addr)
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{
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u16_t ret;
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__asm__ volatile("movw %1, %0;\n\t"
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: "=r"(ret)
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: "m" (*(volatile u16_t *) addr)
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: "memory");
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return ret;
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}
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static ALWAYS_INLINE
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void sys_write32(u32_t data, mm_reg_t addr)
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{
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__asm__ volatile("movl %0, %1;\n\t"
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:
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: "r"(data), "m" (*(volatile u32_t *) addr)
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: "memory");
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}
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static ALWAYS_INLINE
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u32_t sys_read32(mm_reg_t addr)
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{
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u32_t ret;
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__asm__ volatile("movl %1, %0;\n\t"
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: "=r"(ret)
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: "m" (*(volatile u32_t *) addr)
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: "memory");
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return ret;
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}
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static ALWAYS_INLINE
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void sys_set_bit(mem_addr_t addr, unsigned int bit)
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{
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__asm__ volatile("btsl %1, %0;\n\t"
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: "+m" (*(volatile u32_t *) (addr))
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: "Ir" (bit)
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: "memory");
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}
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static ALWAYS_INLINE
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void sys_clear_bit(mem_addr_t addr, unsigned int bit)
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{
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__asm__ volatile("btrl %1, %0;\n\t"
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: "+m" (*(volatile u32_t *) (addr))
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: "Ir" (bit));
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}
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static ALWAYS_INLINE
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int sys_test_bit(mem_addr_t addr, unsigned int bit)
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{
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int ret;
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__asm__ volatile("btl %2, %1;\n\t"
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"sbb %0, %0\n\t"
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: "=r" (ret), "+m" (*(volatile u32_t *) (addr))
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: "Ir" (bit));
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return ret;
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}
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static ALWAYS_INLINE
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int sys_test_and_set_bit(mem_addr_t addr, unsigned int bit)
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{
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int ret;
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__asm__ volatile("btsl %2, %1;\n\t"
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"sbb %0, %0\n\t"
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: "=r" (ret), "+m" (*(volatile u32_t *) (addr))
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: "Ir" (bit));
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return ret;
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}
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static ALWAYS_INLINE
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int sys_test_and_clear_bit(mem_addr_t addr, unsigned int bit)
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{
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int ret;
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__asm__ volatile("btrl %2, %1;\n\t"
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"sbb %0, %0\n\t"
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: "=r" (ret), "+m" (*(volatile u32_t *) (addr))
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: "Ir" (bit));
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return ret;
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}
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#define sys_bitfield_set_bit sys_set_bit
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#define sys_bitfield_clear_bit sys_clear_bit
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#define sys_bitfield_test_bit sys_test_bit
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#define sys_bitfield_test_and_set_bit sys_test_and_set_bit
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#define sys_bitfield_test_and_clear_bit sys_test_and_clear_bit
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASM_INLINE_GCC_PUBLIC_GCC_H */
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