af3a19106a
Some SoC have missing feature selections in their Kconfig. Some others are missing includes of CMSIS-Core headers. Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
177 lines
4.4 KiB
Text
177 lines
4.4 KiB
Text
# LPC LPC55XXX Series
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# Copyright 2019, 2023 NXP
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# SPDX-License-Identifier: Apache-2.0
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choice
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prompt "LPC5500 Series MCU Selection"
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depends on SOC_SERIES_LPC55XXX
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config SOC_LPC55S06
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bool "SOC_LPC55S06 M33"
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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select ARM_TRUSTZONE_M
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select CLOCK_CONTROL
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select HAS_MCUX_IAP if !TRUSTED_EXECUTION_NONSECURE
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select HAS_MCUX_RNG
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config SOC_LPC55S16
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bool "SOC_LPC55S16 M33"
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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select ARM_TRUSTZONE_M
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select CLOCK_CONTROL
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select HAS_MCUX_IAP if !TRUSTED_EXECUTION_NONSECURE
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select HAS_MCUX_MCAN
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select HAS_MCUX_RNG
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config SOC_LPC55S28
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bool "SOC_LPC55S28 M33"
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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select CLOCK_CONTROL
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select HAS_MCUX_IAP
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select HAS_MCUX_LPADC
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select HAS_MCUX_LPC_DMA
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select HAS_MCUX_RNG
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config SOC_LPC55S36
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bool "SOC_LPC55S36 M33"
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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select ARM_TRUSTZONE_M
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select CLOCK_CONTROL
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select HAS_MCUX_MCAN
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select HAS_MCUX_PWM
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config SOC_LPC55S69_CPU0
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bool "SOC_LPC55S69 M33 [CPU 0]"
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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select ARM_TRUSTZONE_M
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select CLOCK_CONTROL
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select HAS_MCUX_IAP
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select HAS_MCUX_LPADC
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select HAS_MCUX_LPC_DMA
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select HAS_MCUX_USB_LPCIP3511
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select HAS_MCUX_CTIMER
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select HAS_MCUX_SCTIMER
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select HAS_MCUX_RNG
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config SOC_LPC55S69_CPU1
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bool "SOC_LPC55S69 M33 [CPU 1]"
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select CPU_CORTEX_M33
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endchoice
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if SOC_SERIES_LPC55XXX
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config SOC_PART_NUMBER_LPC55S06JBD64
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bool
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config SOC_PART_NUMBER_LPC55S16JBD64
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bool
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config SOC_PART_NUMBER_LPC55S16JBD100
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bool
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config SOC_PART_NUMBER_LPC55S28JBD100
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bool
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config SOC_PART_NUMBER_LPC55S36JBD100
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bool
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config SOC_PART_NUMBER_LPC55S69JBD100
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bool
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config SOC_PART_NUMBER_LPC55S69JET98
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bool
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config SOC_PART_NUMBER_LPC55XXX
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string
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default "LPC55S06JBD64" if SOC_PART_NUMBER_LPC55S06JBD64
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default "LPC55S16JBD64" if SOC_PART_NUMBER_LPC55S16JBD64
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default "LPC55S16JBD100" if SOC_PART_NUMBER_LPC55S16JBD100
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default "LPC55S28JBD100" if SOC_PART_NUMBER_LPC55S28JBD100
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default "LPC55S36JBD100" if SOC_PART_NUMBER_LPC55S36JBD100
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default "LPC55S69JBD100" if SOC_PART_NUMBER_LPC55S69JBD100
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default "LPC55S69JET98" if SOC_PART_NUMBER_LPC55S69JET98
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help
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This string holds the full part number of the SoC. It is a hidden
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option that you should not set directly. The part number selection
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choice defines the default value for this string.
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config INIT_PLL0
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bool "Initialize PLL0"
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config INIT_PLL1
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bool "Initialize PLL1"
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default "y"
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depends on !(SOC_LPC55S06 || FLASH)
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help
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In the LPC55XXX Family, this is currently being used to set the
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core clock value at it's highest frequency which clocks at 150MHz.
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Note that flash programming operations are limited to 100MHz, and
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this PLL should not be used as the core clock in those cases.
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 144000000 if INIT_PLL1
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default 96000000
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config SECOND_CORE_MCUX
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bool "LPC55xxx's second core"
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depends on HAS_MCUX
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help
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Indicates the second core will be enabled, and the part will run
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in dual core mode.
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# Workaround for not being able to have commas in macro arguments
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DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition
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config SECOND_CORE_BOOT_ADDRESS_MCUX
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depends on SECOND_CORE_MCUX
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hex "Address the second core will boot at"
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_CPU1_PARTITION))
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help
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This is the address the second core will boot from.
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# Move the LMA for the second core image to be in the flash region of primary
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# core, so that JLink flash will load it correctly.
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config BUILD_OUTPUT_ADJUST_LMA
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depends on SECOND_CORE_MCUX && SOC_LPC55S69_CPU1
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default "0x10000000"
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config LPC55XXX_SRAM_CLOCKS
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bool "CLock LPC SRAM banks"
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default y
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help
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SRAM controllers 1,2,3, and 4 are disabled at reset.
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By default, CMSIS SystemInit will enable the clock to these RAM banks.
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Disable this Kconfig to leave the ram banks untouched out of reset.
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config LPC55XXX_USB_RAM
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bool
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default y
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help
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Some SoC's in the LPC5500 Series do have a dedicated USB RAM.
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By default, USB RAM is assumed to be present.
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Disable this Kconfig in case there is no dedicated USB RAM.
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endif # SOC_SERIES_LPC55XXX
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