a8796ca6ee
add uhc related items to dts. add clock initialization add BM4 if CONFIG_USB_UHC_NXP_KHCI is enabled add pin mux update board related CMakeLists.txt update sdk-ng CMake to include NXP controller drivers update west.yml to contain the hal_nxp pr Signed-off-by: Mark Wang <yichang.wang@nxp.com>
39 lines
1.1 KiB
CMake
39 lines
1.1 KiB
CMake
#
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# Copyright (c) 2019,2024 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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zephyr_library()
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zephyr_library_sources(soc.c)
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zephyr_library_include_directories(
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${ZEPHYR_BASE}/kernel/include
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${ZEPHYR_BASE}/arch/${ARCH}/include
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)
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if(DEFINED CONFIG_LPC55XXX_USB_RAM)
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zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER
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SECTIONS usb.ld)
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zephyr_linker_sources_ifdef(CONFIG_UDC_DRIVER
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SECTIONS usb.ld)
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zephyr_linker_sources_ifdef(CONFIG_UHC_DRIVER
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SECTIONS usb.ld)
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zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
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zephyr_compile_definitions_ifdef(CONFIG_UDC_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
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zephyr_compile_definitions_ifdef(CONFIG_UHC_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
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endif()
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# CMSIS SystemInit allows us to skip enabling clock to SRAM banks via
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# this compiler definition
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if(NOT DEFINED CONFIG_LPC55XXX_SRAM_CLOCKS)
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zephyr_compile_definitions(DONT_ENABLE_DISABLED_RAMBANKS=1)
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endif()
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if (CONFIG_SOC_LPC55S69_CPU0)
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zephyr_sources_ifdef(CONFIG_PM power.c)
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endif()
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zephyr_include_directories(.)
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")
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