86469b1d0b
Make the LSE driving capability configurable for the STM32 series. Fixes #44737. Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
461 lines
10 KiB
Text
461 lines
10 KiB
Text
/*
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* Copyright (c) 2020 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <dt-bindings/clock/stm32wl_clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/lora/sx126x.h>
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#include <dt-bindings/pwm/pwm.h>
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#include <dt-bindings/pwm/stm32_pwm.h>
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#include <freq.h>
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/ {
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chosen {
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zephyr,entropy = &rng;
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zephyr,flash-controller = &flash;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "st,stm32wl-hse-clock";
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/* Expected clock-frequency on the whole series 32MHz */
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clock-frequency = <DT_FREQ_M(32)>;
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status = "disabled";
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(16)>;
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status = "disabled";
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};
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clk_msi: clk-msi {
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#clock-cells = <0>;
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compatible = "st,stm32-msi-clock";
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msi-range = <6>; /* 4MHz (reset value) */
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status = "disabled";
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "st,stm32-lse-clock";
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clock-frequency = <32768>;
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driving-capability = <0>;
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status = "disabled";
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_K(32)>;
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status = "disabled";
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};
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pll: pll {
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#clock-cells = <0>;
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compatible = "st,stm32wb-pll-clock";
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status = "disabled";
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};
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};
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soc {
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flash: flash-controller@58004000 {
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compatible = "st,stm32-flash-controller", "st,stm32wl-flash-controller";
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label = "FLASH_CTRL";
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reg = <0x58004000 0x400>;
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interrupts = <4 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "st,stm32-nv-flash", "soc-nv-flash";
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label = "FLASH_STM32";
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write-block-size = <8>;
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erase-block-size = <2048>;
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/* maximum erase time(ms) for a 2K sector */
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max-erase-time = <25>;
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};
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};
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rcc: rcc@58000000 {
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compatible = "st,stm32wl-rcc";
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#clock-cells = <2>;
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reg = <0x58000000 0x400>;
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label = "STM32_CLK_RCC";
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};
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exti: interrupt-controller@58000800 {
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compatible = "st,stm32-exti";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x58000800 0x400>;
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};
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pinctrl: pin-controller@48000000 {
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compatible = "st,stm32-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x48000000 0x2000>;
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gpioa: gpio@48000000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
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label = "GPIOA";
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};
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gpiob: gpio@48000400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
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label = "GPIOB";
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};
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gpioc: gpio@48000800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
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label = "GPIOC";
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};
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gpioh: gpio@48001c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
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label = "GPIOH";
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};
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};
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lptim1: timers@40007c00 {
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compatible = "st,stm32-lptim";
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40007c00 0x400>;
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interrupts = <39 1>;
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interrupt-names = "wakeup";
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status = "disabled";
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label = "LPTIM_1";
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};
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rtc: rtc@40002800 {
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compatible = "st,stm32-rtc";
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reg = <0x40002800 0x400>;
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interrupts = <42 0>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>;
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prescaler = <32768>;
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status = "disabled";
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label = "RTC_0";
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};
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iwdg: watchdog@40003000 {
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compatible = "st,stm32-watchdog";
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reg = <0x40003000 0x400>;
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label = "IWDG";
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status = "disabled";
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};
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wwdg: watchdog@40002c00 {
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compatible = "st,stm32-window-watchdog";
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reg = <0x40002C00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
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label = "WWDG";
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interrupts = <0 7>;
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status = "disabled";
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};
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usart1: serial@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
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interrupts = <36 0>;
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status = "disabled";
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label = "UART_1";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
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interrupts = <37 0>;
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status = "disabled";
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label = "UART_2";
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};
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lpuart1: serial@40008000 {
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compatible = "st,stm32-lpuart", "st,stm32-uart";
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reg = <0x40008000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
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interrupts = <38 0>;
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status = "disabled";
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label = "LPUART_1";
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};
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i2c1: i2c@40005400 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
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interrupts = <30 0>, <31 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_1";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
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interrupts = <32 0>, <33 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_2";
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};
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i2c3: i2c@40005c00 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
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interrupts = <48 0>, <49 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_3";
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};
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spi1: spi@40013000 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013000 0x400>;
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interrupts = <34 5>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
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status = "disabled";
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label = "SPI_1";
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};
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spi2: spi@40003800 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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interrupts = <35 5>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
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status = "disabled";
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label = "SPI_2";
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};
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subghzspi: spi@58010000 {
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compatible = "st,stm32-spi-subghz", "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x58010000 0x400>;
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interrupts = <44 5>;
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000001>;
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status = "disabled";
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label = "SUBGHZSPI";
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use-subghzspi-nss;
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radio@0 {
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compatible = "st,stm32wl-subghz-radio";
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reg = <0>;
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interrupts = <50 0>;
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spi-max-frequency = <12000000>;
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status = "disabled";
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label = "subghz-radio";
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};
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};
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adc1: adc@40012400 {
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compatible = "st,stm32-adc";
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reg = <0x40012400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
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interrupts = <18 0>;
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status = "disabled";
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label = "ADC_1";
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#io-channel-cells = <1>;
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has-temp-channel;
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has-vref-channel;
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};
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dac1: dac@40007400 {
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compatible = "st,stm32-dac";
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reg = <0x40007400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
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status = "disabled";
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label = "DAC_1";
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#io-channel-cells = <1>;
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};
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timers1: timers@40012c00 {
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compatible = "st,stm32-timers";
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reg = <0x40012c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
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interrupts = <23 0>, <24 0>, <25 0>, <26 0>;
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interrupt-names = "brk", "up", "trgcom", "cc";
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st,prescaler = <0>;
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status = "disabled";
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label = "TIMERS_1";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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label = "PWM_1";
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#pwm-cells = <3>;
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};
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};
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timers2: timers@40000000 {
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compatible = "st,stm32-timers";
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reg = <0x40000000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
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interrupts = <27 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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label = "TIMERS_2";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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label = "PWM_2";
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#pwm-cells = <3>;
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};
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};
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timers16: timers@40014400 {
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compatible = "st,stm32-timers";
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reg = <0x40014400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
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interrupts = <28 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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label = "TIMERS_16";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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label = "PWM_16";
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#pwm-cells = <3>;
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};
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};
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timers17: timers@40014800 {
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compatible = "st,stm32-timers";
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reg = <0x40014800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
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interrupts = <29 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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label = "TIMERS_17";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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label = "PWM_17";
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#pwm-cells = <3>;
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};
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};
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aes: aes@58001800 {
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compatible = "st,stm32-aes";
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reg = <0x58001800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00020000>;
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interrupts = <51 0>;
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status = "disabled";
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label = "AES";
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};
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rng: rng@58001000 {
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compatible = "st,stm32-rng";
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reg = <0x58001000 0x400>;
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interrupts = <52 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00040000>;
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health-test-magic = <0x17590abc>;
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health-test-config = <0xaa74>;
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status = "disabled";
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label = "RNG";
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};
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dma1: dma@40020000 {
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compatible = "st,stm32-dma-v2";
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#dma-cells = <3>;
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reg = <0x40020000 0x400>;
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interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
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dma-requests = <7>;
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dma-offset = <0>;
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status = "disabled";
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label = "DMA_1";
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};
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dma2: dma@40020400 {
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compatible = "st,stm32-dma-v2";
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#dma-cells = <3>;
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reg = <0x40020400 0x400>;
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interrupts = <54 0 55 0 56 0 57 0 58 0 59 0 60 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
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dma-requests = <7>;
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dma-offset = <7>;
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status = "disabled";
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label = "DMA_2";
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};
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dmamux1: dmamux@40020800 {
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compatible = "st,stm32-dmamux";
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#dma-cells = <3>;
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reg = <0x40020800 0x400>;
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interrupts = <61 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x4>;
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dma-channels = <14>;
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dma-generators = <4>;
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dma-requests= <38>;
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status = "disabled";
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label = "DMAMUX_1";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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