7c2d7d7b69
For now, only the 32-bit subarchitecture supports memory protection. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
34 lines
839 B
C
34 lines
839 B
C
/*
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* Copyright (c) 2011-2015, Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for the ia32 platform
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*
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* This module provides routines to initialize and support board-level hardware
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* for the ia32 platform.
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*/
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#include <kernel.h>
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#include "soc.h"
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#include <drivers/uart.h>
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#include <device.h>
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#include <init.h>
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#include <ia32/mmustructs.h>
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#include <linker/linker-defs.h>
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#ifdef CONFIG_X86_MMU
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MMU_BOOT_REGION(CONFIG_LOAPIC_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
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MMU_BOOT_REGION(DT_IOAPIC_BASE_ADDRESS, MB(1), MMU_ENTRY_WRITE);
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#ifdef CONFIG_HPET_TIMER
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MMU_BOOT_REGION(CONFIG_HPET_TIMER_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
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#endif
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#ifdef CONFIG_ETH_E1000
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MMU_BOOT_REGION(DT_ETH_E1000_BASE_ADDRESS, KB(128), MMU_ENTRY_WRITE);
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#endif
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#endif /* CONFIG_X86_MMU*/
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