6d83738e33
All of the cases of CONFIG_SPI_x_IRQ_PRI should be DT_SPI_x_IRQ_PRI. So go ahead and fix them up. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
61 lines
2.9 KiB
C
61 lines
2.9 KiB
C
/* SoC level DTS fixup file */
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#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_80800_BASE_ADDRESS
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#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_80800_CURRENT_SPEED
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#define CONFIG_UART_NS16550_PORT_0_NAME DT_NS16550_80800_LABEL
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#define DT_UART_NS16550_PORT_0_IRQ ((DT_NS16550_80800_IRQ_0 << 16) | \
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(DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
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(DT_INTEL_CAVS_INTC_78800_IRQ_0 << 0))
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#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_80800_IRQ_0_PRIORITY
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#define DT_UART_NS16550_PORT_0_IRQ_FLAGS DT_NS16550_80800_IRQ_0_SENSE
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#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_80800_CLOCK_FREQUENCY
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#define DT_L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS
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#define DT_L2_SRAM_SIZE CONFIG_SRAM_SIZE * 1024
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#define DT_CAVS_ICTL_BASE_ADDR DT_INTEL_CAVS_INTC_78800_BASE_ADDRESS
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#define DT_CAVS_ICTL_0_IRQ DT_INTEL_CAVS_INTC_78800_IRQ_0
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#define DT_CAVS_ICTL_0_IRQ_PRI DT_INTEL_CAVS_INTC_78800_IRQ_0_PRIORITY
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#define DT_CAVS_ICTL_0_IRQ_FLAGS DT_INTEL_CAVS_INTC_78800_IRQ_0_SENSE
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#define DT_CAVS_ICTL_1_IRQ DT_INTEL_CAVS_INTC_78810_IRQ_0
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#define DT_CAVS_ICTL_1_IRQ_PRI DT_INTEL_CAVS_INTC_78810_IRQ_0_PRIORITY
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#define DT_CAVS_ICTL_1_IRQ_FLAGS DT_INTEL_CAVS_INTC_78810_IRQ_0_SENSE
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#define DT_CAVS_ICTL_2_IRQ DT_INTEL_CAVS_INTC_78820_IRQ_0
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#define DT_CAVS_ICTL_2_IRQ_PRI DT_INTEL_CAVS_INTC_78820_IRQ_0_PRIORITY
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#define DT_CAVS_ICTL_2_IRQ_FLAGS DT_INTEL_CAVS_INTC_78820_IRQ_0_SENSE
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#define DT_CAVS_ICTL_3_IRQ DT_INTEL_CAVS_INTC_78830_IRQ_0
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#define DT_CAVS_ICTL_3_IRQ_PRI DT_INTEL_CAVS_INTC_78830_IRQ_0_PRIORITY
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#define DT_CAVS_ICTL_3_IRQ_FLAGS DT_INTEL_CAVS_INTC_78830_IRQ_0_SENSE
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#define DT_DW_ICTL_BASE_ADDR DT_SNPS_DESIGNWARE_INTC_81800_BASE_ADDRESS
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#define DT_DW_ICTL_IRQ ((DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
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(DT_INTEL_CAVS_INTC_78800_IRQ_0 << 0))
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#define DT_DW_ICTL_IRQ_PRI DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0_PRIORITY
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#define DT_DW_ICTL_IRQ_FLAGS DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0_SENSE
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#define DT_I2C_0_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_80400_BASE_ADDRESS
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#define DT_I2C_0_BITRATE DT_SNPS_DESIGNWARE_I2C_80400_CLOCK_FREQUENCY
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#define CONFIG_I2C_0_NAME DT_SNPS_DESIGNWARE_I2C_80400_LABEL
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#define DT_I2C_0_IRQ ((DT_SNPS_DESIGNWARE_I2C_80400_IRQ_0 << 16) | \
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(DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
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(DT_INTEL_CAVS_INTC_78800_IRQ_0 << 0))
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#define DT_I2C_0_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_80400_IRQ_0_SENSE
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#define DT_I2C_0_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_80400_IRQ_0_PRIORITY
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#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_E000_BASE_ADDRESS
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#define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_E000_LABEL
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#define DT_SPI_0_IRQ ((DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0 << 16) | \
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(DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
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(DT_INTEL_CAVS_INTC_78800_IRQ_0 << 0))
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#define DT_SPI_DW_IRQ_FLAGS DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_SENSE
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#define DT_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_PRIORITY
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/* End of SoC Level DTS fixup file */
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