Tom Burdick 1e9ada4eb9 dma: cavs: Add gpdma derivative of dw dma for cavs ... Intel's adsp needs to set, at a minimum, a clocking bit before the driver can initialize the designware dma controller. In many ways it is the designware dmac IP but with additional registers and functionality added on top of it. So the code structure here follows how the hardware appears to be designed, layered on top of the designware driver. Signed-off-by: Tom Burdick <thomas.burdick@intel.com>		2022-02-21 20:59:08 -05:00
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cavs_v15	arch/xtensa: Use ZSR assignments for the CPU pointer	2022-01-20 12:58:00 -05:00
cavs_v18	arch/xtensa: Use ZSR assignments for the CPU pointer	2022-01-20 12:58:00 -05:00
cavs_v20	arch/xtensa: Use ZSR assignments for the CPU pointer	2022-01-20 12:58:00 -05:00
cavs_v25	dma: cavs: Add gpdma derivative of dw dma for cavs	2022-02-21 20:59:08 -05:00
common	soc: xtensa: Replaced /dev/null in scripts	2022-02-03 07:59:55 -05:00
tools	soc/intel_adsp: cavstool: don't unload driver when --log-only	2022-01-27 05:24:24 -05:00
CMakeLists.txt	xtensa: set toolchain variant per SoC	2020-12-20 14:30:50 -05:00
Kconfig	soc/intel_adsp: Replace trace_out code with a sys_winstream	2022-01-13 14:01:23 -05:00
Kconfig.defconfig	arch/xtensa: Promote adsp RPO/cache utilities to an arch API	2022-01-11 11:53:53 +01:00
Kconfig.soc	soc/xtensa/intel_adsp: Upstream updates	2020-10-21 06:38:53 -04:00