Tom Burdick 1e9ada4eb9 dma: cavs: Add gpdma derivative of dw dma for cavs ... Intel's adsp needs to set, at a minimum, a clocking bit before the driver can initialize the designware dma controller. In many ways it is the designware dmac IP but with additional registers and functionality added on top of it. So the code structure here follows how the hardware appears to be designed, layered on top of the designware driver. Signed-off-by: Tom Burdick <thomas.burdick@intel.com>		2022-02-21 20:59:08 -05:00
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esp32	soc: xtensa: esp32: fixes flash size reference	2022-02-07 13:22:25 -05:00
esp32s2	soc: esp32s2: fix: data cache setup	2021-12-03 16:45:16 -06:00
intel_adsp	dma: cavs: Add gpdma derivative of dw dma for cavs	2022-02-21 20:59:08 -05:00
intel_s1000	arch/xtensa: Use ZSR assignments for the CPU pointer	2022-01-20 12:58:00 -05:00
nxp_adsp	soc: xtensa: cavs-link.ld: add *(.trace_ctx) sections	2021-12-22 17:47:21 -06:00
sample_controller	soc: xtensa/sample_controller: add snippets to linker script	2022-02-10 14:24:50 -05:00
CMakeLists.txt	soc/xtensa/intel_adsp: Upstream updates	2020-10-21 06:38:53 -04:00