292f7454d4
- Move config BUILD_OUTPUT_HEX and CLOK_CONTROL from board deconfig into SoC deconfig - Add clock-frequency in dts to get config SYS_CLOCK_HW_CYCLES_PER_SEC from dts Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
358 lines
7.2 KiB
Text
358 lines
7.2 KiB
Text
/*
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* Copyright (c) 2024-2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
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#include <zephyr/dt-bindings/clock/ra_clock.h>
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#include <zephyr/dt-bindings/pwm/ra_pwm.h>
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/delete-node/ &adc1;
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/delete-node/ &dac1;
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/ {
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soc {
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(256)>;
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};
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ioport6: gpio@400800c0 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x400800c0 0x20>;
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port = <6>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport7: gpio@400800e0 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x400800e0 0x20>;
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port = <7>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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sci1: sci1@40118100 {
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compatible = "renesas,ra-sci";
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interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118100 0x100>;
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clocks = <&pclka MSTPB 30>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <1>;
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status = "disabled";
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};
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};
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sci2: sci2@40118200 {
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compatible = "renesas,ra-sci";
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interrupts = <8 1>, <9 1>, <10 1>, <11 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118200 0x100>;
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clocks = <&pclka MSTPB 29>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <2>;
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status = "disabled";
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};
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};
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sci3: sci3@40118300 {
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compatible = "renesas,ra-sci";
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interrupts = <12 1>, <13 1>, <14 1>, <15 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118300 0x100>;
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clocks = <&pclka MSTPB 28>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <3>;
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status = "disabled";
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};
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};
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sci4: sci4@40118400 {
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compatible = "renesas,ra-sci";
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interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118400 0x100>;
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clocks = <&pclka MSTPB 27>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <4>;
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status = "disabled";
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};
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};
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adc@40170000 {
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channel-count = <11>;
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channel-available-mask = <0x31ff>;
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};
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pwm6: pwm6@40169600 {
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compatible = "renesas,ra-pwm";
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divider = <RA_PWM_SOURCE_DIV_1>;
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channel = <RA_PWM_CHANNEL_6>;
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clocks = <&pclkd MSTPE 25>;
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reg = <0x40169600 0x100>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm7: pwm7@40169700 {
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compatible = "renesas,ra-pwm";
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divider = <RA_PWM_SOURCE_DIV_1>;
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channel = <RA_PWM_CHANNEL_7>;
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clocks = <&pclkd MSTPE 24>;
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reg = <0x40169700 0x100>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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trng: trng {
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compatible = "renesas,ra-sce9-rng";
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status = "disabled";
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};
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};
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clocks: clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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xtal: clock-main-osc {
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compatible = "renesas,ra-cgc-external-clock";
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clock-frequency = <DT_FREQ_M(20)>;
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#clock-cells = <0>;
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status = "disabled";
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};
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hoco: clock-hoco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(20)>;
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#clock-cells = <0>;
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};
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moco: clock-moco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(8)>;
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#clock-cells = <0>;
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};
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loco: clock-loco {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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subclk: clock-subclk {
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compatible = "renesas,ra-cgc-subclk";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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status = "disabled";
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};
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pll: pll {
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compatible = "renesas,ra-cgc-pll";
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#clock-cells = <0>;
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/* PLL */
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clocks = <&hoco>;
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div = <2>;
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mul = <20 0>;
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status = "disabled";
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};
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pll2: pll2 {
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compatible = "renesas,ra-cgc-pll";
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#clock-cells = <0>;
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/* PLL2 */
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div = <2>;
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mul = <20 0>;
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status = "disabled";
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};
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pclkblock: pclkblock@40084000 {
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compatible = "renesas,ra-cgc-pclk-block";
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reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>,
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<0x4008400c 4>, <0x40084010 4>;
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reg-names = "MSTPA", "MSTPB","MSTPC",
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"MSTPD", "MSTPE";
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#clock-cells = <0>;
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clocks = <&pll>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clock-frequency = <200000000>;
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div = <1>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclka: pclka {
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compatible = "renesas,ra-cgc-pclk";
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div = <2>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkb: pclkb {
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compatible = "renesas,ra-cgc-pclk";
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div = <4>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkc: pclkc {
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compatible = "renesas,ra-cgc-pclk";
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div = <4>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkd: pclkd {
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compatible = "renesas,ra-cgc-pclk";
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div = <2>;
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#clock-cells = <2>;
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status = "okay";
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};
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fclk: fclk {
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compatible = "renesas,ra-cgc-pclk";
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div = <4>;
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#clock-cells = <2>;
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status = "okay";
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};
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uclk: uclk {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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clkout: clkout {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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};
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};
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};
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&ioport0 {
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port-irqs = <&port_irq6 &port_irq7 &port_irq8
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&port_irq9 &port_irq10 &port_irq11
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&port_irq12 &port_irq13>;
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port-irq-names = "port-irq6",
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"port-irq7",
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"port-irq8",
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"port-irq9",
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"port-irq10",
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"port-irq11",
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"port-irq12",
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"port-irq13";
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port-irq6-pins = <0>;
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port-irq7-pins = <1>;
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port-irq8-pins = <2>;
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port-irq9-pins = <4>;
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port-irq10-pins = <5>;
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port-irq11-pins = <6>;
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port-irq12-pins = <8>;
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port-irq13-pins = <15>;
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};
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&ioport1 {
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port-irqs = <&port_irq0 &port_irq1 &port_irq2
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&port_irq3 &port_irq4>;
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port-irq-names = "port-irq0",
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"port-irq1",
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"port-irq2",
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"port-irq3",
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"port-irq4";
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port-irq0-pins = <5>;
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port-irq1-pins = <1 4>;
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port-irq2-pins = <0>;
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port-irq3-pins = <10>;
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port-irq4-pins = <11>;
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};
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&ioport2 {
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port-irqs = <&port_irq0 &port_irq1 &port_irq2
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&port_irq3>;
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port-irq-names = "port-irq0",
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"port-irq1",
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"port-irq2",
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"port-irq3";
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port-irq0-pins = <6>;
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port-irq1-pins = <5>;
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port-irq2-pins = <13>;
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port-irq3-pins = <12>;
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};
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&ioport3 {
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port-irqs = <&port_irq5 &port_irq6
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&port_irq8 &port_irq9>;
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port-irq-names = "port-irq5",
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"port-irq6",
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"port-irq8",
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"port-irq9";
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port-irq5-pins = <2>;
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port-irq6-pins = <1>;
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port-irq8-pins = <5>;
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port-irq9-pins = <4>;
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};
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&ioport4 {
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port-irqs = <&port_irq0 &port_irq4 &port_irq5
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&port_irq6 &port_irq7 &port_irq8
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&port_irq9 &port_irq14 &port_irq15>;
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port-irq-names = "port-irq0",
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"port-irq4",
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"port-irq5",
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"port-irq6",
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"port-irq7",
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"port-irq8",
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"port-irq9",
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"port-irq14",
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"port-irq15";
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port-irq0-pins = <0>;
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port-irq4-pins = <2 11>;
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port-irq5-pins = <1 10>;
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port-irq6-pins = <9>;
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port-irq7-pins = <8>;
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port-irq8-pins = <15>;
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port-irq9-pins = <14>;
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port-irq14-pins = <3>;
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port-irq15-pins = <4>;
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};
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&ioport5 {
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port-irqs = <&port_irq11 &port_irq12 &port_irq14>;
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port-irq-names = "port-irq11",
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"port-irq12",
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"port-irq14";
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port-irq11-pins = <1>;
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port-irq12-pins = <2>;
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port-irq14-pins = <5>;
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};
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&ioport7 {
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port-irqs = <&port_irq11>;
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port-irq-names = "port-irq11";
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port-irq11-pins = <8>;
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};
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&dac_global {
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has-output-amplifier;
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};
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