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zephyr/soc/riscv/openisa_rv32m1
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Carlo Caione aec9a8c4be arch: arm: Move ARM code to AArch32 sub-directory 
Before introducing the code for ARM64 (AArch64) we need to relocate the
current ARM code to a new AArch32 sub-directory. For now we can assume
that no code is shared between ARM and ARM64.

There are no functional changes. The code is moved to the new location
and the file paths are fixed to reflect this change.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2019-12-20 11:40:59 -05:00
..
CMakeLists.txt riscv: linker.ld: Port vector table to zephyr_linker_sources() 2019-12-20 08:54:53 -05:00
dts_fixup.h riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
Kconfig kconfig: Clean up header comments and make them consistent 2019-11-04 17:31:27 -05:00
Kconfig.defconfig openisa_rv32m1: kconfig: Remove base address/size symbols 2019-12-11 12:44:47 -06:00
Kconfig.soc kconfig: Clean up header comments and make them consistent 2019-11-04 17:31:27 -05:00
linker.ld arch: arm: Move ARM code to AArch32 sub-directory 2019-12-20 11:40:59 -05:00
soc.c kernel: rename z_arch_ to arch_ 2019-11-07 15:21:46 -08:00
soc.h riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
soc_context.h riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
soc_irq.S riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
soc_offsets.h riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
soc_ri5cy.h riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
soc_zero_riscy.h riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
vector.S riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
vector_table.ld riscv: linker.ld: Port vector table to zephyr_linker_sources() 2019-12-20 08:54:53 -05:00
wdog.S riscv32: rename to riscv 2019-08-02 13:54:48 -07:00