07cb01b079
This breaks down the GPIO controller definition in DTS into multiple entries. This allows these controllers to be referenced by other DTS, and test board overlay files. And also we can remove the entries in the dts fixup file. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
72 lines
3.1 KiB
C
72 lines
3.1 KiB
C
/*
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* Copyright (c) 2018-2019 Intel Corporation Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* SoC level DTS fixup file */
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#define DT_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
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#define DT_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS
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#define DT_RAM_SIZE CONFIG_SRAM_SIZE
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#define DT_ROM_SIZE CONFIG_FLASH_SIZE
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#define DT_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS
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#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_INST_0_NS16550_BASE_ADDRESS
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#define DT_UART_NS16550_PORT_0_SIZE DT_INST_0_NS16550_SIZE
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#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_INST_0_NS16550_CURRENT_SPEED
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#define DT_UART_NS16550_PORT_0_NAME DT_INST_0_NS16550_LABEL
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#define DT_UART_NS16550_PORT_0_IRQ DT_INST_0_NS16550_IRQ_0
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#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_INST_0_NS16550_IRQ_0_PRIORITY
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#define DT_UART_NS16550_PORT_0_IRQ_FLAGS DT_INST_0_NS16550_IRQ_0_SENSE
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#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_INST_0_NS16550_CLOCK_FREQUENCY
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#define DT_UART_NS16550_PORT_0_PCIE DT_INST_0_NS16550_PCIE
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#ifdef DT_NS16550_0_PCP
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#define DT_UART_NS16550_PORT_0_PCP DT_NS16550_0_PCP
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#endif
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#define DT_UART_NS16550_PORT_1_BASE_ADDR DT_INST_1_NS16550_BASE_ADDRESS
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#define DT_UART_NS16550_PORT_1_SIZE DT_INST_1_NS16550_SIZE
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#define DT_UART_NS16550_PORT_1_BAUD_RATE DT_INST_1_NS16550_CURRENT_SPEED
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#define DT_UART_NS16550_PORT_1_NAME DT_INST_1_NS16550_LABEL
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#define DT_UART_NS16550_PORT_1_IRQ DT_INST_1_NS16550_IRQ_0
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#define DT_UART_NS16550_PORT_1_IRQ_PRI DT_INST_1_NS16550_IRQ_0_PRIORITY
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#define DT_UART_NS16550_PORT_1_IRQ_FLAGS DT_INST_1_NS16550_IRQ_0_SENSE
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#define DT_UART_NS16550_PORT_1_CLK_FREQ DT_INST_1_NS16550_CLOCK_FREQUENCY
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#define DT_UART_NS16550_PORT_1_PCIE DT_INST_1_NS16550_PCIE
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#ifdef DT_NS16550_1_PCP
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#define DT_UART_NS16550_PORT_1_PCP DT_NS16550_1_PCP
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#endif
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#define DT_UART_NS16550_PORT_2_BASE_ADDR DT_INST_2_NS16550_BASE_ADDRESS
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#define DT_UART_NS16550_PORT_2_SIZE DT_INST_2_NS16550_SIZE
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#define DT_UART_NS16550_PORT_2_BAUD_RATE DT_INST_2_NS16550_CURRENT_SPEED
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#define DT_UART_NS16550_PORT_2_NAME DT_INST_2_NS16550_LABEL
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#define DT_UART_NS16550_PORT_2_IRQ DT_INST_2_NS16550_IRQ_0
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#define DT_UART_NS16550_PORT_2_IRQ_PRI DT_INST_2_NS16550_IRQ_0_PRIORITY
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#define DT_UART_NS16550_PORT_2_IRQ_FLAGS DT_INST_2_NS16550_IRQ_0_SENSE
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#define DT_UART_NS16550_PORT_2_CLK_FREQ DT_INST_2_NS16550_CLOCK_FREQUENCY
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#define DT_UART_NS16550_PORT_2_PCIE DT_INST_2_NS16550_PCIE
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#ifdef DT_NS16550_2_PCP
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#define DT_UART_NS16550_PORT_2_PCP DT_NS16550_2_PCP
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#endif
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#define DT_UART_NS16550_PORT_3_BASE_ADDR DT_INST_3_NS16550_BASE_ADDRESS
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#define DT_UART_NS16550_PORT_3_SIZE DT_INST_3_NS16550_SIZE
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#define DT_UART_NS16550_PORT_3_BAUD_RATE DT_INST_3_NS16550_CURRENT_SPEED
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#define DT_UART_NS16550_PORT_3_NAME DT_INST_3_NS16550_LABEL
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#define DT_UART_NS16550_PORT_3_IRQ DT_INST_3_NS16550_IRQ_0
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#define DT_UART_NS16550_PORT_3_IRQ_PRI DT_INST_3_NS16550_IRQ_0_PRIORITY
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#define DT_UART_NS16550_PORT_3_IRQ_FLAGS DT_INST_3_NS16550_IRQ_0_SENSE
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#define DT_UART_NS16550_PORT_3_CLK_FREQ DT_INST_3_NS16550_CLOCK_FREQUENCY
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#define DT_UART_NS16550_PORT_3_PCIE DT_INST_3_NS16550_PCIE
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#ifdef DT_NS16550_3_PCP
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#define DT_UART_NS16550_PORT_3_PCP DT_NS16550_3_PCP
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#endif
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/* End of SoC Level DTS fixup file */
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