38f0b05b99
This commit fixes the following problems with the RPU device tree: 1. The core type of the RPU of ZynqMP SoC is Cortex-R5F, not Cortex-R4. 2. RPU and APU use different interrupt controllers (PL390 GICv1 and GIC-400 GICv2, respectively) mapped to the same CPU local bus address region but with different offsets for the distributor and CPU interrupt control register sets. The GIC address mapping specified by the current dts is that of an APU and does not apply to the PL390 GICv1 of an RPU (refer to the "Zynq UltraScale+ Devices Register Reference" document from Xilinx for more information). For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
35 lines
557 B
Plaintext
35 lines
557 B
Plaintext
/*
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* Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/xilinx/zynqmp.dtsi>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-r5f";
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reg = <0>;
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};
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};
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soc {
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interrupt-parent = <&gic>;
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gic: interrupt-controller@f9000000 {
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compatible = "arm,gic";
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reg = <0xf9000000 0x1000>,
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<0xf9001000 0x100>;
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interrupt-controller;
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#interrupt-cells = <4>;
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label = "GIC";
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status = "okay";
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};
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};
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};
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