492e890cd6
This adds a rather primitive driver for use with the Intra-DSP Communication (IDC) on the DSP on certain Intel SoCs. The IDC generates interrupts from one core to another by writing to certain registers. This is also being utilized as the scheduler IPI since it can interrupt other cores. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
37 lines
1 KiB
C
37 lines
1 KiB
C
/*
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* Copyright (c) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_H_
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#define ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_H_
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/* For use with the IPM driver */
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#define IPM_CAVS_IDC_DEV_NAME cavs_idc
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#define IPM_CAVS_IDC_ID_MASK \
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(CAVS_IDC_TYPE(CAVS_IDC_TYPE_MASK) | \
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CAVS_IDC_HEADER(CAVS_IDC_HEADER_MASK))
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/* IDC message type. */
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#define CAVS_IDC_TYPE_SHIFT 24U
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#define CAVS_IDC_TYPE_MASK 0x7FU
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#define CAVS_IDC_TYPE(x) \
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(((x) & CAVS_IDC_TYPE_MASK) << CAVS_IDC_TYPE_SHIFT)
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/* IDC message header. */
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#define CAVS_IDC_HEADER_MASK 0xFFFFFFU
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#define CAVS_IDC_HEADER(x) ((x) & CAVS_IDC_HEADER_MASK)
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/* IDC message extension. */
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#define CAVS_IDC_EXTENSION_MASK 0x3FFFFFFFU
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#define CAVS_IDC_EXTENSION(x) ((x) & CAVS_IDC_EXTENSION_MASK)
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/* Scheduler IPI message (type 0x7F, header 'IPI' in ascii) */
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#define IPM_CAVS_IDC_MSG_SCHED_IPI_DATA 0
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#define IPM_CAVS_IDC_MSG_SCHED_IPI_ID \
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(CAVS_IDC_TYPE(0x7FU) | CAVS_IDC_HEADER(0x495049U))
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#endif /* ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_H_ */
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