301208329b
We should not set PLLSRC bits here. It is done by LL_PLL_ConfigSystemClock_* functions which are called later. Also, PREDIV1 setting should not be restricted to HSE only. Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
84 lines
2.1 KiB
C
84 lines
2.1 KiB
C
/*
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*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <drivers/clock_control.h>
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#include <sys/util.h>
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#include <drivers/clock_control/stm32_clock_control.h>
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#include "clock_stm32_ll_common.h"
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#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
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/**
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* @brief fill in pll configuration structure
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*/
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void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
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{
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/*
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* PLL MUL
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* 2 -> LL_RCC_PLL_MUL_2 -> 0x00000000
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* 3 -> LL_RCC_PLL_MUL_3 -> 0x00040000
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* 4 -> LL_RCC_PLL_MUL_4 -> 0x00080000
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* ...
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* 16 -> LL_RCC_PLL_MUL_16 -> 0x00380000
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*/
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pllinit->PLLMul = ((CONFIG_CLOCK_STM32_PLL_MULTIPLIER - 2)
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<< RCC_CFGR_PLLMUL_Pos);
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/*
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* PLL PREDIV
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* 1 -> LL_RCC_PREDIV_DIV_1 -> 0x00000000
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* 2 -> LL_RCC_PREDIV_DIV_2 -> 0x00000001
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* 3 -> LL_RCC_PREDIV_DIV_3 -> 0x00000002
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* ...
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* 16 -> LL_RCC_PREDIV_DIV_16 -> 0x0000000F
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*/
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#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
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/*
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* PREDIV1 support is a specific RCC configuration present on
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* following SoCs: STM32F04xx, STM32F07xx, STM32F09xx,
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* STM32F030xC, STM32F302xE, STM32F303xE and STM32F39xx
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* cf Reference manual for more details
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*/
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pllinit->PLLDiv = CONFIG_CLOCK_STM32_PLL_PREDIV1 - 1;
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#else
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pllinit->Prediv = CONFIG_CLOCK_STM32_PLL_PREDIV - 1;
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#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
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}
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#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
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/**
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* @brief Activate default clocks
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*/
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void config_enable_default_clocks(void)
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{
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#ifndef CONFIG_SOC_SERIES_STM32F3X
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#if defined(CONFIG_EXTI_STM32) || defined(CONFIG_USB_DC_STM32)
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/* Enable System Configuration Controller clock. */
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LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG);
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#endif
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#else
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#if defined(CONFIG_USB_DC_STM32) && defined(SYSCFG_CFGR1_USB_IT_RMP)
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/* Enable System Configuration Controller clock. */
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/* SYSCFG is required to remap IRQ to avoid conflicts with CAN */
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/* cf §14.1.3, RM0316 */
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
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#endif
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#endif /* !CONFIG_SOC_SERIES_STM32F3X */
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}
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/**
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* @brief Function kept for driver genericity
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*/
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void LL_RCC_MSI_Disable(void)
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{
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/* Do nothing */
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}
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