d929e874c2
The SoC node has compatibles for the specific SoC in place, having the same compatible at the top level is technically a conflict and the top-level one should really just be about the board. Remove the SoC related compatibles at the top-level. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
72 lines
1.1 KiB
Plaintext
72 lines
1.1 KiB
Plaintext
/*
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* Copyright (c) 2017 VNG IoT Lab Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <nordic/nrf51822_qfac.dtsi>
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/ {
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model = "VNG VBLUno51 BLE board";
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compatible = "vng,vbluno51";
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,bt-mon-uart = &uart0;
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zephyr,bt-c2h-uart = &uart0;
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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};
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/* These aliases are provided for compatibility with samples */
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aliases {
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led0 = &led0;
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sw0 = &button0;
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};
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leds {
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compatible = "gpio-leds";
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/* green led */
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led0: led_0 {
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gpios = <&gpio0 7 0>;
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label = "LED";
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};
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};
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buttons {
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/* Push button switch 0 KEY1 */
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compatible = "gpio-keys";
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button0: button_0 {
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/* gpio flags need validation */
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gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
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label = "Button";
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};
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};
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};
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&gpiote {
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status = "okay";
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};
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&gpio0 {
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status = "okay";
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};
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&uart0 {
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current-speed = <115200>;
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status = "okay";
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tx-pin = <10>;
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rx-pin = <11>;
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rts-pin = <12>;
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cts-pin = <13>;
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <I2C_BITRATE_FAST>;
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sda-pin = <29>;
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scl-pin = <30>;
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};
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