f2ccd2b00a
This commit adds support for TF-M to the MPS2 AN521. When the CONFIG_BUILD_WITH_TFM flag is set, a secure and non-secure processing environment image pair will be generated, with the Zephyr application image running on the non-secure side. The secure and non-secure binary images will be signed for use with the BL2 secure bootloader. An additional .hex file is also generated to enable running QEMU with the AN521 binaries, `tfm_qemu.hex`, which can be executed with the `-t run` option with west, or `run` with ninja or make. When configured for use with TF-M, the `mps2_an521_nonsecure` board definition should be used. Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
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451 lines
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.. _mps2_an521_board:
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ARM MPS2+ AN521
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###############
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Overview
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********
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The mps2_an521 board configuration is used by Zephyr applications that run
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on the MPS2+ AN521 board. It provides support for the MPS2+ AN521 ARM Cortex-M33
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CPU and the following devices:
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- Nested Vectored Interrupt Controller (NVIC)
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- System Tick System Clock (SYSTICK)
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- Cortex-M System Design Kit GPIO
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- Cortex-M System Design Kit UART
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.. image:: img/mps2_an521.png
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:width: 666px
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:align: center
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:height: 546px
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:alt: ARM MPS2+ AN521
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In addition to enabling actual hardware usage, this board configuration can
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also use QEMU to emulate the AN521 platform running on the MPS2+.
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More information about the board can be found at the `MPS2 FPGA Website`_.
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.. note::
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This board configuration makes no claims about its suitability for use
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with actual MPS2 hardware systems using AN521, or any other hardware
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system. It has been tested on actual hardware, but its primary purpose is
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for use with QEMU and unit tests for the ARM Cortex-M33.
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Hardware
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********
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ARM MPS2+ AN521 provides the following hardware components:
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- ARM Cortex-M33
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- Soft Macro Model (SMM) implementation of SSE-200 subsystem
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- Memory
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- 16MB internal memory SRAM
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- 8KB of NVM code
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- 224MB code memory
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- Debug
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- P-JTAG, SWD & 16-bit TRACE
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- UART port
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- Interface
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- AHB GPIO connected to the EXP port
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- UART
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- SPI
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- I2C
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- I2S
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- Color LCD serial interface
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- Ethernet
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- VGA
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- On-board Peripherals
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- Color LCD
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- 8 LEDs
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- 8 Switches
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- External SSRAM1, SSRAM2 & SSRAM3
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- SMSC9220
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- CS42L52
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User push buttons
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=================
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The mps2_an521 board provides the following user push buttons:
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- ON power on
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- nSRST: Cortex-M33 system reset and CoreSight debug reset
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- USERPB0 and USERPB1: User defined buttons
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Supported Features
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===================
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The mps2_an521 board configuration supports the following hardware features:
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| NVIC | on-chip | nested vector interrupt controller |
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+-----------+------------+-------------------------------------+
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| SYSTICK | on-chip | systick |
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+-----------+------------+-------------------------------------+
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| UART | on-chip | serial port-polling; |
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| | | serial port-interrupt |
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+-----------+------------+-------------------------------------+
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| PINMUX | on-chip | pinmux |
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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+-----------+------------+-------------------------------------+
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| WATCHDOG | on-chip | watchdog |
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+-----------+------------+-------------------------------------+
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| TIMER | on-chip | timer |
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+-----------+------------+-------------------------------------+
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Other hardware features are not currently supported by the port.
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See the `MPS2 FPGA Website`_ for a complete list of MPS2+ AN521 board hardware
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features.
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The default configuration can be found in the defconfig file:
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``boards/arm/mps2_an521/mps2_an521_defconfig``.
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Interrupt Controller
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====================
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MPS2+ AN521 is a Cortex-M33 based SoC and has 15 fixed exceptions and 77 IRQs.
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A Cortex-M33-based board uses vectored exceptions. This means each exception
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calls a handler directly from the vector table.
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Zephyr provides handlers for exceptions 1-7, 11, 12, 14, and 15, as listed
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in the following table:
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+------+------------+----------------+--------------------------+
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| Exc# | Name | Remarks | Used by Zephyr Kernel |
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+======+============+================+==========================+
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| 1 | Reset | | system initialization |
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+------+------------+----------------+--------------------------+
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| 2 | NMI | | system fatal error |
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+------+------------+----------------+--------------------------+
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| 3 | Hard fault | | system fatal error |
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+------+------------+----------------+--------------------------+
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| 4 | MemManage | MPU fault | system fatal error |
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+------+------------+----------------+--------------------------+
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| 5 | Bus | | system fatal error |
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+------+------------+----------------+--------------------------+
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| 6 | Usage | Undefined | system fatal error |
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| | fault | instruction, | |
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| | | or switch | |
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| | | attempt to ARM | |
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| | | mode | |
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+------+------------+----------------+--------------------------+
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| 7 | SecureFault| Unauthorized | system fatal error |
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| | | access to | |
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| | | secure region | |
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| | | from ns space | |
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+------+------------+----------------+--------------------------+
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| 8 | Reserved | | not handled |
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+------+------------+----------------+--------------------------+
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| 9 | Reserved | | not handled |
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+------+------------+----------------+--------------------------+
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| 10 | Reserved | | not handled |
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+------+------------+----------------+--------------------------+
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| 11 | SVC | | context switch and |
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| | | | software interrupts |
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+------+------------+----------------+--------------------------+
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| 12 | Debug | | system fatal error |
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| | monitor | | |
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+------+------------+----------------+--------------------------+
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| 13 | Reserved | | not handled |
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+------+------------+----------------+--------------------------+
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| 14 | PendSV | | context switch |
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+------+------------+----------------+--------------------------+
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| 15 | SYSTICK | | system clock |
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+------+------------+----------------+--------------------------+
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| 16 | Reserved | | not handled |
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+------+------------+----------------+--------------------------+
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| 17 | Reserved | | not handled |
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+------+------------+----------------+--------------------------+
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| 18 | Reserved | | not handled |
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+------+------------+----------------+--------------------------+
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Pin Mapping
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===========
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The ARM MPS2+ AN521 Board has 4 CMSDK AHB GPIO controllers. Each providing 16
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bits of IO. These controllers are responsible for pin-muxing, input/output,
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pull-up, etc.
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All GPIO controller pins are exposed via the following sequence of pin numbers:
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- Pins 0 - 15 are for GPIO0
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- Pins 16 - 31 are for GPIO1
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- Pins 32 - 47 are for GPIO2
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- Pins 48 - 51 are for GPIO3
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Mapping from the ARM MPS2+ AN521 Board pins to GPIO controllers:
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.. rst-class:: rst-columns
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- D0 : EXT_0
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- D1 : EXT_4
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- D2 : EXT_2
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- D3 : EXT_3
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- D4 : EXT_1
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- D5 : EXT_6
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- D6 : EXT_7
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- D7 : EXT_8
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- D8 : EXT_9
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- D9 : EXT_10
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- D10 : EXT_12
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- D11 : EXT_13
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- D12 : EXT_14
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- D13 : EXT_11
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- D14 : EXT_15
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- D15 : EXT_5
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- D16 : EXT_16
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- D17 : EXT_17
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- D18 : EXT_18
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- D19 : EXT_19
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- D20 : EXT_20
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- D21 : EXT_21
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- D22 : EXT_22
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- D23 : EXT_23
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- D24 : EXT_24
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- D25 : EXT_25
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- D26 : EXT_26
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- D27 : EXT_30
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- D28 : EXT_28
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- D29 : EXT_29
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- D30 : EXT_27
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- D31 : EXT_32
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- D32 : EXT_33
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- D33 : EXT_34
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- D34 : EXT_35
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- D35 : EXT_36
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- D36 : EXT_38
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- D37 : EXT_39
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- D38 : EXT_40
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- D39 : EXT_44
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- D40 : EXT_41
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- D41 : EXT_31
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- D42 : EXT_37
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- D43 : EXT_42
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- D44 : EXT_43
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- D45 : EXT_45
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- D46 : EXT_46
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- D47 : EXT_47
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- D48 : EXT_48
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- D49 : EXT_49
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- D50 : EXT_50
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- D51 : EXT_51
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Peripheral Mapping:
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.. rst-class:: rst-columns
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- UART_3_RX : D0
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- UART_3_TX : D1
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- SPI_3_CS : D10
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- SPI_3_MOSI : D11
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- SPI_3_MISO : D12
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- SPI_3_SCLK : D13
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- I2C_3_SDA : D14
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- I2C_3_SCL : D15
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- UART_4_RX : D26
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- UART_4_TX : D30
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- SPI_4_CS : D36
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- SPI_4_MOSI : D37
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- SPI_4_MISO : D38
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- SPI_4_SCK : D39
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- I2C_4_SDA : D40
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- I2C_4_SCL : D41
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For mode details refer to `MPS2+ AN521 Technical Reference Manual (TRM)`_.
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LED
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============
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MPS2+ has 8 built-in LEDs connected to Serial Configuration Controller (SCC).
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.. note:: The SCC register CFG_REG1 Bits [7:0] for LEDa, 0 = OFF 1 = ON.
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System Clock
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============
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MPS2+ AN521 has several clocks connected:
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.. rst-class:: rst-columns
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- MAINCLK : 20MHz
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- SYSCLK : 20MHz
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- S32KCLK : 32kHz
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- TRACECLK : 20MHz
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- SWCLKTCK : 20MHz
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- TRACECLKIN : 20MHz
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Serial Port
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===========
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The MPS2+ AN521 has five UARTs. The Zephyr console output by default, uses
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UART0, which is J10 on the board.
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UART2 is reserved. And UART 1, 3 and 4 are alt-functions on the EXP ports.
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Security components
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===================
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- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is used to define
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secure and non-secure memory maps. By default, all of the memory space is
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defined to be secure accessible only
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- Secure and Non-secure peripherals via the Peripheral Protection Controller
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(PPC). Peripherals can be assigned as secure or non-secure accessible
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- Secure boot
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- Secure `AMBA®`_ interconnect
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Serial Configuration Controller (SCC)
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=====================================
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The MPS2+ AN521 implements a Serial Configuration Control (SCC) register.
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The purpose of this register is to allow individual control of clocks,
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reset-signals and interrupts to peripherals, and pin-muxing, and the LEDs and
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switches.
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Programming and Debugging
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*************************
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MPS2+ AN521 supports the v8m security extension, and by default boots to the
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secure state.
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When building a secure/non-secure application, the secure application will
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have to set the idau/sau and mpc configuration to permit access from the
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non-secure application before jumping.
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The following system components are required to be properly configured during the
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secure firmware:
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- AHB5 TrustZone Memory Protection Controller (MPC)
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- AHB5 TrustZone Peripheral Protection Controller (PPC)
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- Implementation-Defined Attribution Unit (IDAU)
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For more details refer to `Corelink SSE-200 Subsystem`_.
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Flashing
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========
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MPS2+ AN521 provides:
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- A USB connection to the host computer, which exposes a Mass Storage
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- A Serial Port which is J10 on MPS2+ board
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Building a secure only application
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----------------------------------
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You can build applications in the usual way. Here is an example for
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the :ref:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: mps2_an521
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:goals: build
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Open a serial terminal (minicom, putty, etc.) with the following settings:
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- Speed: 115200
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- Data: 8 bits
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- Parity: None
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- Stop bits: 1
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Reset the board, and you should see the following message on the corresponding
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serial port:
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.. code-block:: console
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Hello World! mps2_an521
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Building a secure/non-secure with Trusted Firmware
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--------------------------------------------------
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The process requires five steps:
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1. Build Trusted Firmware (tfm).
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2. Import it as a library to the Zephyr source folder.
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3. Build Zephyr with a non-secure configuration.
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4. Merge the two binaries together and sign them.
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5. Concatenate the bootloader with the signed image blob.
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To build tfm, refer to `Trusted Firmware M Guide`_. Follow the build steps
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for the AN521 target while replacing the platform with
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``-DTARGET_PLATFORM=AN521`` and the compiler (if required) with
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``-DCOMPILER=GNUARM``.
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Copy over tfm as a library to the Zephyr project source and create a shortcut
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for the secure veneers and necessary header files. All files are in the install
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folder after TF-M has been built.
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Uploading an application to MPS2+ AN521
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---------------------------------------
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Applications can be in elf, hex or bin format. The binaries are flashed when
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the board boots up, using files stored on the on-board Micro SD card. The
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Motherboard Configuration Controller (MCC) is responsible for loading the FPGA
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image and binaries.
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Connect the MPS2+ to your host computer using the USB port. You should see a
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USB connection exposing a Mass Storage (``V2M_MPS2`` by default).
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The update requires 3 steps:
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1. Copy application files to ``<MPS2 device name>/SOFTWARE/``.
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2. Open ``<MPS2 device name>/MB/HBI0263C/AN521/images.txt``.
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3. Update the ``AN521/images.txt`` file as follows:
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.. code-block:: bash
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TITLE: Versatile Express Images Configuration File
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[IMAGES]
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TOTALIMAGES: 1 ;Number of Images (Max: 32)
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IMAGE0ADDRESS: 0x10000000 ;Please select the required executable program
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IMAGE0FILE: \SOFTWARE\zephyr.bin
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Reset the board, and you should see the following message on the corresponding
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serial port:
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.. code-block:: console
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Hello World! mps2_an521
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.. note:: Refer to the tfm_integration sample for more details about integrating with TF-M and multiple images scenario.
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.. _MPS2 FPGA Website:
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https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/mps2
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.. _MPS2+ AN521 Technical Reference Manual (TRM):
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http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/DAI0521C_Example_SSE200_Subsystem_for_MPS2plus.pdf
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.. _Cortex M33 Generic User Guide:
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http://infocenter.arm.com/help/topic/com.arm.doc.100235_0004_00_en/arm_cortex_m33_dgug_100235_0004_00_en.pdf
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.. _Trusted Firmware M Guide:
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https://git.trustedfirmware.org/trusted-firmware-m.git/tree/docs/user_guides/tfm_build_instruction.rst
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.. _Corelink SSE-200 Subsystem:
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https://developer.arm.com/products/system-design/subsystems/corelink-sse-200-subsystem
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.. _IDAU:
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https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau
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.. _AMBA®:
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https://developer.arm.com/products/architecture/system-architectures/amba
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