c802cc8920
Replaces custom runtime calls to map memory. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
164 lines
3.6 KiB
C
164 lines
3.6 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <sys/device_mmio.h>
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#include <drivers/pcie/pcie.h>
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#ifdef CONFIG_ACPI
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#include <arch/x86/acpi.h>
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#endif
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#ifdef CONFIG_PCIE_MSI
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#include <drivers/pcie/msi.h>
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#endif
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/* PCI Express Extended Configuration Mechanism (MMIO) */
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#define MAX_PCI_BUS_SEGMENTS 4
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static struct {
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uint32_t start_bus;
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uint32_t n_buses;
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uint8_t *mmio;
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} bus_segs[MAX_PCI_BUS_SEGMENTS];
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static void pcie_mm_init(void)
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{
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#ifdef CONFIG_ACPI
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struct acpi_mcfg *m = z_acpi_find_table(ACPI_MCFG_SIGNATURE);
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if (m != NULL) {
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int n = (m->sdt.len - sizeof(*m)) / sizeof(m->pci_segs[0]);
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for (int i = 0; i < n && i < MAX_PCI_BUS_SEGMENTS; i++) {
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size_t size;
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uintptr_t phys_addr;
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bus_segs[i].start_bus = m->pci_segs[i].start_bus;
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bus_segs[i].n_buses = 1 + m->pci_segs[i].end_bus
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- m->pci_segs[i].start_bus;
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phys_addr = m->pci_segs[i].base_addr;
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/* 32 devices & 8 functions per bus, 4k per device */
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size = bus_segs[i].n_buses * (32 * 8 * 4096);
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device_map((mm_reg_t *)&bus_segs[i].mmio, phys_addr,
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size, K_MEM_CACHE_NONE);
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}
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}
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#endif
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}
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static inline void pcie_mm_conf(pcie_bdf_t bdf, unsigned int reg,
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bool write, uint32_t *data)
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{
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if (bus_segs[0].mmio == NULL) {
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pcie_mm_init();
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}
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for (int i = 0; i < ARRAY_SIZE(bus_segs); i++) {
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int off = PCIE_BDF_TO_BUS(bdf) - bus_segs[i].start_bus;
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if (off >= 0 && off < bus_segs[i].n_buses) {
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bdf = PCIE_BDF(off,
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PCIE_BDF_TO_DEV(bdf),
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PCIE_BDF_TO_FUNC(bdf));
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volatile uint32_t *regs
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= (void *)&bus_segs[0].mmio[bdf << 4];
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if (write) {
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regs[reg] = *data;
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} else {
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*data = regs[reg];
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}
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}
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}
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}
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/* Traditional Configuration Mechanism */
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#define PCIE_X86_CAP 0xCF8U /* Configuration Address Port */
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#define PCIE_X86_CAP_BDF_MASK 0x00FFFF00U /* b/d/f bits */
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#define PCIE_X86_CAP_EN 0x80000000U /* enable bit */
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#define PCIE_X86_CAP_WORD_MASK 0x3FU /* 6-bit word index .. */
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#define PCIE_X86_CAP_WORD_SHIFT 2U /* .. is in CAP[7:2] */
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#define PCIE_X86_CDP 0xCFCU /* Configuration Data Port */
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/*
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* Helper function for exported configuration functions. Configuration access
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* ain't atomic, so spinlock to keep drivers from clobbering each other.
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*/
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static inline void pcie_io_conf(pcie_bdf_t bdf, unsigned int reg,
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bool write, uint32_t *data)
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{
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static struct k_spinlock lock;
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k_spinlock_key_t k;
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bdf &= PCIE_X86_CAP_BDF_MASK;
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bdf |= PCIE_X86_CAP_EN;
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bdf |= (reg & PCIE_X86_CAP_WORD_MASK) << PCIE_X86_CAP_WORD_SHIFT;
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k = k_spin_lock(&lock);
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sys_out32(bdf, PCIE_X86_CAP);
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if (write) {
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sys_out32(*data, PCIE_X86_CDP);
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} else {
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*data = sys_in32(PCIE_X86_CDP);
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}
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sys_out32(0U, PCIE_X86_CAP);
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k_spin_unlock(&lock, k);
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}
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static inline void pcie_conf(pcie_bdf_t bdf, unsigned int reg,
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bool write, uint32_t *data)
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{
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#ifdef CONFIG_PCIE_MMIO_CFG
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pcie_mm_conf(bdf, reg, write, data);
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#else
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pcie_io_conf(bdf, reg, write, data);
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#endif
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}
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/* these functions are explained in include/drivers/pcie/pcie.h */
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uint32_t pcie_conf_read(pcie_bdf_t bdf, unsigned int reg)
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{
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uint32_t data = 0;
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pcie_conf(bdf, reg, false, &data);
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return data;
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}
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void pcie_conf_write(pcie_bdf_t bdf, unsigned int reg, uint32_t data)
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{
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pcie_conf(bdf, reg, true, &data);
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}
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#ifdef CONFIG_PCIE_MSI
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/* these functions are explained in include/drivers/pcie/msi.h */
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uint32_t pcie_msi_map(unsigned int irq)
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{
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ARG_UNUSED(irq);
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return 0xFEE00000U; /* standard delivery to BSP local APIC */
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}
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uint16_t pcie_msi_mdr(unsigned int irq)
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{
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unsigned char vector = Z_IRQ_TO_INTERRUPT_VECTOR(irq);
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return 0x4000U | vector; /* edge triggered */
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}
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#endif
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