Commit graph

7 commits

Author SHA1 Message Date
Andrew Boie
c802cc8920 x86: pcie: use device_map() for MMIO config access
Replaces custom runtime calls to map memory.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-17 11:38:18 +02:00
Andy Ross
0e20eafe7a arch/x86: Make sure PCI mmio is initialized before page tables
The page table initialization needs a populated PCI MMIO
configuration, and that is lazy-evaluated.  We aren't guaranteed that
a driver already hit that path, so be sure to call it explicitly.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2020-07-08 12:34:09 +02:00
Andy Ross
7c6d8aa58e arch/x86: Add support for PCI MMIO configuration access
The traditional IO Port configuration mechanism was technically
deprecated about 15 years ago when PCI Express started shipping.
While frankly the MMIO support is significantly more complicated and
no more performant in practice, Zephyr should have support for current
standards.  And (particularly complicated) devices do exist in the
wild whose extended capability pointers spill beyond the 256 byte area
allowed by the legacy mechanism.  Zephyr will want drivers for those
some day.

Also, Windows and Linux use MMIO access, which means that's what
system vendors validate.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2020-06-23 13:07:39 +02:00
Kumar Gala
a1b77fd589 zephyr: replace zephyr integer types with C99 types
git grep -l 'u\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g"
	git grep -l 's\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g"

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-06-08 08:23:57 -05:00
Charles E. Youse
d25ef6ed44 arch/x86/pcie: use Z_IRQ_TO_INTERRUPT_VECTOR() macro
The _irq_to_interrupt_vector[] array shouldn't be accessed directly,
as there is a macro for this.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-09-15 11:33:47 +08:00
Charles E. Youse
dff016b53c arch/x86: move include/arch/x86/arch.h to ia32/arch.h
Making room for the Intel64 subarch in this tree. This header is
32-bit specific and so it's relocated, and references rewritten
to find it in its new location.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-02 19:30:00 -04:00
Charles E. Youse
e039053546 uart/ns16550, drivers/pcie: add PCI(e) support
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.

The NS16550 UART driver is modified to use pcie.

pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.

This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.

Deficiencies:

64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.

The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-04-17 10:50:05 -07:00