We've reversed core launch order to workaround issue of
ARConnect initialization interfere with secondary cores
startup (we don't want to workaround it in runtime as it's
only possible in case of debug session).
However it bring us new issues with the simulation run:
- mismatch arcnum (core ID) with ARConnect ID
- mismatch arcnum (core ID) with CPU name in nSIM instruction traces
To avoid these issues let's use direct core order for simulation
runs.
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
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