aaa119d757
This adds micfil node for NPX i.MX8MP SOC. Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
160 lines
3.3 KiB
Text
160 lines
3.3 KiB
Text
/*
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* Copyright 2021, 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/clock/imx_ccm.h>
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#include <xtensa/xtensa.dtsi>
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#include <mem.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx6";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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clic: interrupt-controller@0 {
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compatible = "cdns,xtensa-core-intc";
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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};
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};
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sram0: memory@92400000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x92400000 DT_SIZE_K(512)>;
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};
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sram1: memory@92c00000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x92c00000 DT_SIZE_K(512)>;
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};
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mclk1: mclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <12288000>;
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};
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soc {
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irqsteer: interrupt-controller@30a80000 {
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compatible = "nxp,irqsteer-intc";
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reg = <0x30a80000 DT_SIZE_K(64)>;
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#size-cells = <0>;
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#address-cells = <1>;
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master0: interrupt-controller@0 {
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compatible = "nxp,irqsteer-master";
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 19 0 0>;
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};
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master1: interrupt-controller@1 {
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compatible = "nxp,irqsteer-master";
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reg = <1>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 20 0 0>;
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};
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master2: interrupt-controller@2 {
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compatible = "nxp,irqsteer-master";
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reg = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 21 0 0>;
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};
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};
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ccm: ccm@30380000 {
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compatible = "nxp,imx-ccm";
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reg = <0x30380000 DT_SIZE_K(64)>;
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#clock-cells = <3>;
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};
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sdma3: dma@30e00000 {
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compatible = "nxp,sdma";
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reg = <0x30e00000 DT_SIZE_K(64)>;
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interrupt-parent = <&master1>;
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interrupts = <2 0 0>;
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#dma-cells = <2>;
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status = "disabled";
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};
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sai3: dai@30c30000 {
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compatible = "nxp,dai-sai";
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reg = <0x30c30000 DT_SIZE_K(64)>;
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mclk-is-output;
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clocks = <&mclk1>;
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clock-names = "mclk1";
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interrupt-parent = <&master1>;
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interrupts = <18>;
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dai-index = <3>;
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/* DMA event source, peripheral type */
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dmas = <&sdma3 5 5>, <&sdma3 4 5>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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micfil: micfil@30ca0000 {
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compatible = "nxp,dai-micfil";
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reg = <0x30ca0000 DT_SIZE_K(64)>;
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dai-index = <2>;
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dmas = <&sdma3 24 6>;
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fifo-depth = <32>;
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status = "disabled";
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};
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iomuxc: iomuxc@30330000 {
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compatible = "nxp,imx-iomuxc";
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reg = <0x30330000 DT_SIZE_K(64)>;
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status = "okay";
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pinctrl: pinctrl {
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status = "okay";
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compatible = "nxp,imx8mp-pinctrl";
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};
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};
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/*
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* For now only UART4 is supported and
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* tested with the serial driver
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*/
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uart4: uart@30a60000 {
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compatible = "nxp,imx-iuart";
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reg = <0x30a60000 0x10000>;
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/* TODO: This INTID is just a dummy
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* until we can support UART interrupts
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*/
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interrupt-parent = <&master0>;
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interrupts = <29 0 0>;
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clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>;
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status = "disabled";
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};
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mailbox0: mailbox@30e70000 {
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compatible = "nxp,imx-mu";
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reg = <0x30e70000 0x10000>;
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interrupt-parent = <&clic>;
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interrupts = <7 0 0>;
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rdc = <0>;
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status = "disabled";
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};
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};
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};
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