/*
 * Copyright 2021, 2023 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <zephyr/dt-bindings/clock/imx_ccm.h>
#include <xtensa/xtensa.dtsi>
#include <mem.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "cdns,tensilica-xtensa-lx6";
			reg = <0>;

			#address-cells = <1>;
			#size-cells = <0>;

			clic: interrupt-controller@0 {
				compatible = "cdns,xtensa-core-intc";
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <3>;
			};
		};
	};

	sram0: memory@92400000 {
		device_type = "memory";
		compatible = "mmio-sram";
		reg = <0x92400000 DT_SIZE_K(512)>;
	};

	sram1: memory@92c00000 {
		device_type = "memory";
		compatible = "mmio-sram";
		reg = <0x92c00000 DT_SIZE_K(512)>;
	};

	mclk1: mclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <12288000>;
	};

	soc {
		irqsteer: interrupt-controller@30a80000 {
			compatible = "nxp,irqsteer-intc";
			reg = <0x30a80000 DT_SIZE_K(64)>;

			#size-cells = <0>;
			#address-cells = <1>;

			master0: interrupt-controller@0 {
				compatible = "nxp,irqsteer-master";
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupts-extended = <&clic 19 0 0>;
			};

			master1: interrupt-controller@1 {
				compatible = "nxp,irqsteer-master";
				reg = <1>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupts-extended = <&clic 20 0 0>;
			};

			master2: interrupt-controller@2 {
				compatible = "nxp,irqsteer-master";
				reg = <2>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupts-extended = <&clic 21 0 0>;
			};
		};

		ccm: ccm@30380000 {
			compatible = "nxp,imx-ccm";
			reg = <0x30380000 DT_SIZE_K(64)>;
			#clock-cells = <3>;
		};

		sdma3: dma@30e00000 {
			compatible = "nxp,sdma";
			reg = <0x30e00000 DT_SIZE_K(64)>;
			interrupt-parent = <&master1>;
			interrupts = <2 0 0>;
			#dma-cells = <2>;
			status = "disabled";
		};

		sai3: dai@30c30000 {
			compatible = "nxp,dai-sai";
			reg = <0x30c30000 DT_SIZE_K(64)>;

			mclk-is-output;
			clocks = <&mclk1>;
			clock-names = "mclk1";

			interrupt-parent = <&master1>;
			interrupts = <18>;
			dai-index = <3>;
			/* DMA event source, peripheral type */
			dmas = <&sdma3 5 5>, <&sdma3 4 5>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		micfil: micfil@30ca0000 {
			compatible = "nxp,dai-micfil";
			reg = <0x30ca0000 DT_SIZE_K(64)>;
			dai-index = <2>;
			dmas = <&sdma3 24 6>;
			fifo-depth = <32>;
			status = "disabled";
		};

		iomuxc: iomuxc@30330000 {
			compatible = "nxp,imx-iomuxc";
			reg = <0x30330000 DT_SIZE_K(64)>;
			status = "okay";
			pinctrl: pinctrl {
				status = "okay";
				compatible = "nxp,imx8mp-pinctrl";
			};
		};

		/*
		 * For now only UART4 is supported and
		 * tested with the serial driver
		 */
		uart4: uart@30a60000 {
			compatible = "nxp,imx-iuart";
			reg = <0x30a60000 0x10000>;
			/* TODO: This INTID is just a dummy
			 * until we can support UART interrupts
			 */
			interrupt-parent = <&master0>;
			interrupts = <29 0 0>;
			clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>;
			status = "disabled";
		};

		mailbox0: mailbox@30e70000 {
			compatible = "nxp,imx-mu";
			reg = <0x30e70000 0x10000>;
			interrupt-parent = <&clic>;
			interrupts = <7 0 0>;
			rdc = <0>;
			status = "disabled";
		};
	};
};