205a8fed79
MCX has more port modules which requires updating the pinctrl driver Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
103 lines
2.7 KiB
C
103 lines
2.7 KiB
C
/*
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* Copyright 2022-2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_kinetis_pinmux
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/logging/log.h>
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#include <fsl_clock.h>
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LOG_MODULE_REGISTER(pinctrl_kinetis, CONFIG_PINCTRL_LOG_LEVEL);
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/* Port register addresses. */
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static PORT_Type *ports[] = {
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(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porta)),
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(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portb)),
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(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portc)),
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#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 3
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(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portd)),
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#endif
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#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 4
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(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porte)),
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#endif
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#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 5
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(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portf)),
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#endif
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};
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#define PIN(mux) (((mux) & 0xFC00000) >> 22)
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#define PORT(mux) (((mux) & 0xF0000000) >> 28)
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#define PINCFG(mux) ((mux) & Z_PINCTRL_KINETIS_PCR_MASK)
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struct pinctrl_mcux_config {
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const struct device *clock_dev;
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clock_control_subsys_t clock_subsys;
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};
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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uintptr_t reg)
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{
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for (uint8_t i = 0; i < pin_cnt; i++) {
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PORT_Type *base = ports[PORT(pins[i])];
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uint8_t pin = PIN(pins[i]);
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uint16_t mux = PINCFG(pins[i]);
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base->PCR[pin] = (base->PCR[pin] & (~Z_PINCTRL_KINETIS_PCR_MASK)) | mux;
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}
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return 0;
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}
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/* Kinetis pinmux driver binds to the same DTS nodes,
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* and handles clock init. Only bind to these nodes if pinmux driver
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* is disabled.
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*/
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static int pinctrl_mcux_init(const struct device *dev)
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{
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const struct pinctrl_mcux_config *config = dev->config;
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int err;
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if (!device_is_ready(config->clock_dev)) {
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LOG_ERR("clock control device not ready");
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return -ENODEV;
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}
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err = clock_control_on(config->clock_dev, config->clock_subsys);
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if (err) {
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LOG_ERR("failed to enable clock (err %d)", err);
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return -EINVAL;
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}
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return 0;
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}
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#if DT_NODE_HAS_STATUS(DT_INST(0, nxp_kinetis_sim), okay)
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#define PINCTRL_MCUX_DT_INST_CLOCK_SUBSYS(n) \
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CLK_GATE_DEFINE(DT_INST_CLOCKS_CELL(n, offset), \
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DT_INST_CLOCKS_CELL(n, bits))
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#else
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#define PINCTRL_MCUX_DT_INST_CLOCK_SUBSYS(n) \
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DT_INST_CLOCKS_CELL(n, name)
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#endif
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#define PINCTRL_MCUX_INIT(n) \
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static const struct pinctrl_mcux_config pinctrl_mcux_##n##_config = {\
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
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.clock_subsys = (clock_control_subsys_t) \
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PINCTRL_MCUX_DT_INST_CLOCK_SUBSYS(n), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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&pinctrl_mcux_init, \
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NULL, \
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NULL, &pinctrl_mcux_##n##_config, \
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PRE_KERNEL_1, \
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CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
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NULL);
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DT_INST_FOREACH_STATUS_OKAY(PINCTRL_MCUX_INIT)
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