5dad944351
The NXP S32 QSPI controller acts as an interface to up to two serial flash memory devices, each with up to eight bidirectional data lines, depending on the platform. It is based on a LUT enginee to interface through commands with different memory types including flash NOR and Hyperram. This patch adds support for the QSPI in S32K344 which supports a single memory device (side A) with up to four bidirectional data lines and SDR only. Nevertheless, the memory controller is implemented flexible enough to be extended to support more feature-rich QSPI blocks. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
35 lines
666 B
Plaintext
35 lines
666 B
Plaintext
# Memory controller configuration options
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# Copyright (c) 2020 Teslabs Engineering S.L.
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# SPDX-License-Identifier: Apache-2.0
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menuconfig MEMC
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bool "Memory controller drivers [EXPERIMENTAL]"
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select EXPERIMENTAL
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help
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Add support for memory controllers
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if MEMC
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module = MEMC
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module-str = memc
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source "subsys/logging/Kconfig.template.log_config"
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config MEMC_INIT_PRIORITY
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int "Initialization priority"
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default 0
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help
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Memory controllers initialization priority.
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source "drivers/memc/Kconfig.stm32"
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source "drivers/memc/Kconfig.mcux"
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source "drivers/memc/Kconfig.sam"
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source "drivers/memc/Kconfig.sifive"
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source "drivers/memc/Kconfig.nxp_s32"
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endif
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